公开(公告)号：US20050101134A1

公开(公告)日：2005-05-12

申请号：US10704498

申请日：2003-11-06

Applicant: Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Robert Chau ,  Robert Turkot

Inventor： Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Robert Chau ,  Robert Turkot

IPC: C23F1/02 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/302 ,  H01L21/461

CPC classification number: C23F1/02 ,  H01L21/32134 ,  H01L21/823842

Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.

Abstract translation: 描述了蚀刻金属层的方法。 该方法包括在基底上形成金属层，然后将金属层的一部分暴露于包含直径超过金属层厚度的活性成分的湿式蚀刻化学物质。

公开(公告)号：US20050064616A1

公开(公告)日：2005-03-24

申请号：US10669064

申请日：2003-09-23

Applicant: Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

Inventor： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L29/786 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

Abstract: A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

Abstract translation: 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US20050009311A1

公开(公告)日：2005-01-13

申请号：US10916191

申请日：2004-08-09

Applicant: John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob Jensen

Inventor： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob Jensen

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

公开(公告)号：US06743683B2

公开(公告)日：2004-06-01

申请号：US10008683

申请日：2001-12-04

Applicant: Chris E. Barns ,  Mark Doczy

Inventor： Chris E. Barns ,  Mark Doczy

IPC: H01L21336

CPC classification number: H01L29/66545 ,  H01L21/3212 ,  H01L29/495

Abstract: Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.

公开(公告)号：US06696345B2

公开(公告)日：2004-02-24

申请号：US10041539

申请日：2002-01-07

Applicant: Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

Inventor： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

IPC: H01R424

CPC classification number: H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

Abstract translation: 描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。 栅电极结构具有三层金属栅电极和多晶硅层。 第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。 第二金属层用于设定栅电极结构的功函数。 第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。制造栅极电极结构的方法包括形成足够厚的三个金属层，以使得每个层提供屏障和所述功能设定功能 而且还足够薄以使得可以进行随后的湿蚀刻而没有金属层的过度底切。 在注入和退火工艺期间，多晶硅层用作金属层上的保护掩模，以保护底层硅衬底与植入过程中使用的掺杂剂相互作用。

公开(公告)号：US06664173B2

公开(公告)日：2003-12-16

申请号：US10044443

申请日：2002-01-09

Applicant: Brian Doyle ,  Mark Doczy ,  Pat Stokley

Inventor： Brian Doyle ,  Mark Doczy ,  Pat Stokley

IPC: H01L213205

CPC classification number: H01L21/32139 ,  H01L21/0332 ,  H01L21/28132 ,  H01L21/823864 ,  Y10S438/947 ,  Y10S438/95

Abstract: An electrical element may be made by providing a hardmask unit that has a double gate stack with a first gate layer, a first hardmask layer formed over the first gate layer, a second gate layer formed over the first hardmask layer, and a second hardmask layer formed over the second gate layer. A first spacer for a first element is formed at a location at least partially determined by the presence of the second hardmask layer, and a second structure for a second element is formed at a location at least partially determined by the presence of the first hardmask layer.

Abstract translation: 电元件可以通过提供一种硬掩模单元来制造，所述硬掩模单元具有双栅极堆叠，其具有第一栅极层，形成在第一栅极层上的第一硬掩模层，形成在第一硬掩模层上的第二栅极层，以及第二硬掩模层 形成在第二栅极层上。 用于第一元件的第一间隔件至少部分地由第二硬掩模层的存在确定的位置形成，并且用于第二元件的第二结构形成在至少部分地由第一硬掩模层的存在确定的位置处 。

公开(公告)号：US06620713B2

公开(公告)日：2003-09-16

申请号：US10038410

申请日：2002-01-02

Applicant: Reza Arghavani ,  Robert Chau ,  Mark Doczy ,  Brian Roberds

Inventor： Reza Arghavani ,  Robert Chau ,  Mark Doczy ,  Brian Roberds

IPC: H01L213205

CPC classification number: H01L21/28176 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31683 ,  H01L29/4925 ,  H01L29/517

Abstract: Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.

Abstract translation: 制造半导体器件的方法 半导体器件包括衬底，形成在衬底上的高k栅介质层和沉积在高k栅介质层上的无氢栅电极，其中无氢栅电极是导电的。 该方法包括在衬底上沉积高k栅极电介质层，在栅极电介质层上溅射栅电极并处理栅电极使得栅电极是导电的。

公开(公告)号：US07754552B2

公开(公告)日：2010-07-13

申请号：US10629127

申请日：2003-07-29

Applicant: Chris E. Barns ,  Justin K. Brask ,  Mark Doczy

Inventor： Chris E. Barns ,  Justin K. Brask ,  Mark Doczy

IPC: H01L21/338

CPC classification number: H01L29/66545

Abstract: A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the polysilicon gate structure 14 from the formation of silicide or etch byproducts. Either the silicide or the etch byproducts or their combination may block the ensuing polysilicon etch which is needed to remove the polysilicon gate structure and to thereafter replace it with an appropriate metal gate technology.

Abstract translation: 在金属栅极替换技术中，可以在多晶硅栅极结构上形成并保持硬掩模。 硬掩模（例如氮化物硬掩模）的维护可以保护多晶硅栅极结构14免受硅化物或蚀刻副产物的形成。 硅化物或蚀刻副产物或它们的组合可以阻止除去多晶硅栅极结构所需的随后的多晶硅蚀刻，然后用适当的金属栅极技术代替它。

公开(公告)号：US07528025B2

公开(公告)日：2009-05-05

申请号：US11986510

申请日：2007-11-21

Applicant: Justin K. Brask ,  Brian S. Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

Inventor： Justin K. Brask ,  Brian S. Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC: H01L21/338

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract translation: 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US07439113B2

公开(公告)日：2008-10-21

申请号：US10889535

申请日：2004-07-12

Applicant: Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

Inventor： Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

IPC: H01L29/78

CPC classification number: H01L21/823842

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

Abstract translation: 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。 可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。