公开(公告)号：US10096496B2

公开(公告)日：2018-10-09

申请号：US15495832

申请日：2017-04-24

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh ,  Sergey G. Belostotskiy

IPC: H01L21/76 ,  H01L21/67 ,  H01L21/3065 ,  H01J37/32 ,  C23C16/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/683 ,  H01L21/02

Abstract: Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.

公开(公告)号：US10062585B2

公开(公告)日：2018-08-28

申请号：US15285214

申请日：2016-10-04

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky

IPC: H01L21/67 ,  H01J37/32 ,  C23C16/455 ,  C23C16/50

CPC classification number: H01L21/67069 ,  C23C16/45565 ,  C23C16/50 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32715 ,  H01J2237/334

Abstract: Described processing chambers may include a chamber housing at least partially defining an interior region of a semiconductor processing chamber. The chamber housing may include a lid. The chamber may include a pedestal configured to support a substrate within a processing region of the chamber. The chamber may also include a first showerhead coupled with an electrical source. The first showerhead may be positioned within the semiconductor processing chamber between the lid and the processing region. The chamber may also include a first dielectric faceplate positioned within the semiconductor processing chamber between the first showerhead and the processing region. The chamber may include a second showerhead coupled with electrical ground and positioned within the semiconductor processing chamber between the first dielectric faceplate and the processing region. The chamber may further include a second dielectric faceplate positioned within the semiconductor processing chamber between the first dielectric faceplate and the second showerhead.

公开(公告)号：US20180240654A1

公开(公告)日：2018-08-23

申请号：US15957827

申请日：2018-04-19

Applicant: Applied Materials, Inc.

Inventor： Soonam Park ,  Yufei Zhu ,  Edwin C. Suarez ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Jiayin Huang

IPC: H01J37/32 ,  C23C16/44 ,  G01J3/02 ,  C23C16/50 ,  C23C16/52 ,  C23C16/455 ,  C23C16/452

CPC classification number: H01L21/32136 ,  C23C16/4405 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/50 ,  C23C16/52 ,  G01J3/0218 ,  G01J3/443 ,  H01J37/32082 ,  H01J37/32532 ,  H01J37/3255 ,  H01J37/32935 ,  H01J37/32963 ,  H01J37/32972 ,  H01J37/3299 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/67069 ,  H01L22/26

Abstract: In an embodiment, a plasma source includes a first electrode, configured for transfer of one or more plasma source gases through first perforations therein; an insulator, disposed in contact with the first electrode about a periphery of the first electrode; and a second electrode, disposed with a periphery of the second electrode against the insulator such that the first and second electrodes and the insulator define a plasma generation cavity. The second electrode is configured for movement of plasma products from the plasma generation cavity therethrough toward a process chamber. A power supply provides electrical power across the first and second electrodes to ignite a plasma with the one or more plasma source gases in the plasma generation cavity to produce the plasma products. One of the first electrode, the second electrode and the insulator includes a port that provides an optical signal from the plasma.

公开(公告)号：US10020170B2

公开(公告)日：2018-07-10

申请号：US15084299

申请日：2016-03-29

Applicant: Applied Materials, Inc.

Inventor： Jennifer Y. Sun ,  Biraja P. Kanungo ,  Dmitry Lubomirsky

IPC: C23C4/10 ,  H01J37/32 ,  H01L21/02 ,  C04B41/87 ,  C04B41/00 ,  C04B41/50 ,  C23C4/11 ,  C23C4/134 ,  H01L21/67

CPC classification number: H01J37/32495 ,  C04B41/009 ,  C04B41/5042 ,  C04B41/87 ,  C23C4/11 ,  C23C4/134 ,  H01J37/32477 ,  H01L21/02 ,  H01L21/67017 ,  Y10T428/24413 ,  Y10T428/2495 ,  Y10T428/24975 ,  Y10T428/252 ,  C04B35/10 ,  C04B35/565 ,  C04B41/4527 ,  C04B41/5032

Abstract: A method includes feeding powder comprising a yttrium oxide into a plasma spraying system, wherein the powder comprises a majority of donut-shaped particles, each of the donut-shaped particles having a spherical body with indentations on opposite sides of the spherical body. The method further includes plasma spray coating an article to apply a ceramic coating onto the article, wherein the ceramic coating comprises the yttrium oxide, wherein the donut-shaped particles cause the ceramic coating to have an improved morphology and a decreased porosity as compared to powder particles of other shapes, wherein the improved surface morphology comprises a reduced amount of surface nodules.

公开(公告)号：US10008366B2

公开(公告)日：2018-06-26

申请号：US15259401

申请日：2016-09-08

Applicant: Applied Materials, Inc.

Inventor： Sang Won Kang ,  Nicholas Celeste ,  Dmitry Lubomirsky ,  Peter Hillman ,  Douglas Brenton Hayden ,  Dongqing Yang

IPC: H01L21/302 ,  H01L21/461 ,  H01J37/32

CPC classification number: H01J37/3244 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32522 ,  H01J37/32724 ,  H01J37/32862

Abstract: Embodiments of the present disclosure generally provide improved methods for processing substrates with improved process stability, increased mean wafers between clean, and/or improved within wafer uniformity. One embodiment provides a method for seasoning one or more chamber components in a process chamber. The method includes placing a dummy substrate in the process chamber, flowing a processing gas mixture to the process chamber to react with the dummy substrate and generate a byproduct on the dummy substrate, and annealing the dummy substrate to sublimate the byproduct while at least one purge conduit of the process chamber is closed.

公开(公告)号：US20180096821A1

公开(公告)日：2018-04-05

申请号：US15285331

申请日：2016-10-04

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/683

Abstract: Described processing chambers may include a chamber housing at least partially defining an interior region of the semiconductor processing chamber. The chambers may include a pedestal. The chambers may include a first showerhead positioned between the lid and the processing region, and may include a faceplate positioned between the first showerhead and the processing region. The chambers may also include a second showerhead positioned within the chamber between the faceplate and the processing region of the semiconductor processing chamber. The second showerhead may include at least two plates coupled together to define a volume between the at least two plates. The at least two plates may at least partially define channels through the second showerhead, and each channel may be characterized by a first diameter at a first end of the channel and may be characterized by a plurality of ports at a second end of the channel.

公开(公告)号：US20180057356A1

公开(公告)日：2018-03-01

申请号：US15649597

申请日：2017-07-13

Applicant: Applied Materials, Inc.

Inventor： Leonard Tedeschi ,  Lili Ji ,  Olivier Joubert ,  Dmitry Lubomirsky ,  Philip Allan Kraus ,  Daniel T. McCormick

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/67

CPC classification number: B81B7/0058 ,  B81B2201/047 ,  B81C1/00031 ,  B81C1/00412 ,  C23C16/4401 ,  C23C16/52 ,  H01L21/67288

Abstract: Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, one or more micro sensors are mounted on wafer processing equipment, and are capable of measuring material deposition and removal rates in real-time. The micro sensors are selectively exposed such that a sensing layer of a micro sensor is protected by a mask layer during active operation of another micro sensor, and the protective mask layer may be removed to expose the sensing layer when the other micro sensor reaches an end-of-life. Other embodiments are also described and claimed.

公开(公告)号：US20180025900A1

公开(公告)日：2018-01-25

申请号：US15217651

申请日：2016-07-22

Applicant: Applied Materials, Inc.

Inventor： Soonam Park ,  Mang-Mang Ling ,  Toan Q. Tran ,  Dmitry Lubomirsky

IPC: H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/02057 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: Methods of removing contamination from the surface of a substrate are described. The etch selectively removes alkali metals and alkali earth metals from substrates. The alkali metals may include sodium, lithium, rubidium or potassium and the alkali earth metals may include calcium. For example, the etch may remove contaminants by generating and then desorbing volatile chemical species from the substrate. A hydrogen-and-oxygen-containing precursor or combination of precursors is flowed into a remote plasma to form plasma effluents. The plasma effluents are then flowed into the substrate processing region to react with the substrate and remove an alkali metal and/or an alkali earth metal from the surface of the substrate. No local plasma excites the plasma effluents in embodiments.

公开(公告)号：US09837249B2

公开(公告)日：2017-12-05

申请号：US15394583

申请日：2016-12-29

Applicant: Applied Materials, Inc.

Inventor： Satoru Kobayashi ,  Soonam Park ,  Dmitry Lubomirsky ,  Hideo Sugai

IPC: H01J7/24 ,  H01J37/32 ,  H01J37/244 ,  H01J19/80 ,  H05B41/16

CPC classification number: H01J37/32229 ,  H01J7/24 ,  H01J19/80 ,  H01J37/244 ,  H01J37/32201 ,  H01J37/32302 ,  H01J37/32311 ,  H01J37/32935 ,  H01J37/3299 ,  H05B41/16

Abstract: A system provides post-match control of microwaves in a radial waveguide. The system includes the radial waveguide, and a signal generator that provides first and second microwave signals that have a common frequency. The signal generator adjusts a phase offset between the first and second signals in response to a correction signal. The system also includes first and second electronics sets, each of which amplifies a respective one of the first and second microwave signals. The system transmits the amplified, first and second microwave signals into the radial waveguide, and matches an impedance of the amplified microwave signals to an impedance presented by the waveguide. The system also includes at least two monitoring antennas disposed within the waveguide. A signal controller receives analog signals from the monitoring antennas, determines the digital correction signal based at least on the analog signals, and transmits the correction signal to the signal generator.

公开(公告)号：US09741593B2

公开(公告)日：2017-08-22

申请号：US14820365

申请日：2015-08-06

Applicant: Applied Materials, Inc.

Inventor： David Benjaminson ,  Dmitry Lubomirsky

IPC: H02G1/08 ,  H01L21/67 ,  H01L21/324 ,  H01L21/687

CPC classification number: H01L21/67103 ,  H01L21/3247 ,  H01L21/68785 ,  H01L22/12

Abstract: A workpiece holder includes a puck having a cylindrical axis, a radius about the cylindrical axis, and a thickness. At least a top surface of the puck is substantially planar, and the puck defines one or more thermal breaks. Each thermal break is a radial recess that intersects at least one of the top surface and a bottom surface of the cylindrical puck. The radial recess has a thermal break depth that extends through at least half of the puck thickness, and a thermal break radius that is at least one-half of the puck radius. A method of processing a wafer includes processing the wafer with a first process that provides a first center-to-edge process variation, and subsequently, processing the wafer with a second process that provides a second center-to-edge process variation that substantially compensates for the first center-to-edge process variation.