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    Methods for filling high aspect ratio trenches in semiconductor layers
    81.
    发明授权
    Methods for filling high aspect ratio trenches in semiconductor layers 有权
    填充半导体层高纵横比沟槽的方法

    公开(公告)号：US07259079B2

    公开(公告)日：2007-08-21

    申请号：US11047476

    申请日：2005-01-31

    Applicant: Jingyi Bai ,  Weimin Li ,  William S. Budge

    Inventor： Jingyi Bai ,  Weimin Li ,  William S. Budge

    IPC: H01L21/76 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

    CPC classification number: H01L21/76224 ,  H01L21/76229

    Abstract: Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims.

    Abstract translation: 提供了在半导体层中填充高纵横比沟槽的方法。 该方法利用HDP-CVD工艺用沟槽填充材料填充沟槽。 在这些方法中，气流和RF偏压被选择以提供对蚀刻比的高蚀刻，同时沟槽被部分填充。 然后选择气体流量和RF偏压，以在沟槽完全填充时提供低的沉积比。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交的理解是不会用于解释或限制权利要求的范围或含义。

    Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials
    82.
    发明授权
    Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials 有权
    使用旋涂，光图案化，层间介电材料形成中间半导体器件结构的方法

    公开(公告)号：US07060637B2

    公开(公告)日：2006-06-13

    申请号：US10435791

    申请日：2003-05-12

    Applicant: Weimin Li ,  Gurtej S. Sandhu

    Inventor： Weimin Li ,  Gurtej S. Sandhu

    IPC: H01L21/47 ,  C08J7/04

    CPC classification number: G03F7/095 ,  G03F7/0757 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/311 ,  Y10T428/31663

    Abstract: A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously unusable. The photopatternable, spin-on material is applied as a layer to a semiconductor substrate. The cap layer and a photoresist layer are each formed over the photopatternable layer. The cap layer absorbs or reflects radiation and protects the photopatternable layer from a first wavelength of radiation used in patterning the photoresist layer. The photopatternable, spin-on material is convertible to a silicon dioxide-based material upon exposure to a second wavelength of radiation.

    Abstract translation: 能够使光可图案化的旋涂材料用于以前不可用的波长形成半导体器件结构的盖层。 将可光刻图案的旋涂材料作为层施加到半导体衬底。 覆盖层和光致抗蚀剂层各自形成在光图案化层上。 盖层吸收或反射辐射，并保护光致图案层免受用于图案化光致抗蚀剂层的第一波长的辐射。 照射图案化的旋涂材料在暴露于第二波长辐射时可转换为二氧化硅基材料。

    Chemical treatment of semiconductor substrates
    83.
    发明授权
    Chemical treatment of semiconductor substrates 失效

    公开(公告)号：US07008885B2

    公开(公告)日：2006-03-07

    申请号：US10913555

    申请日：2004-08-06

    Applicant: Li Li ,  Weimin Li

    Inventor： Li Li ,  Weimin Li

    IPC: H01L21/31

    CPC classification number: H01L21/316 ,  H01L21/76232 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76837 ,  Y10S438/902

    Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers. The liquid may be applied to the substrate by chemical vapor deposition or by spin-applying.

    Methods for filling high aspect ratio trenches in semiconductor layers
    85.
    发明授权
    Methods for filling high aspect ratio trenches in semiconductor layers 失效
    填充半导体层高纵横比沟槽的方法

    公开(公告)号：US06982207B2

    公开(公告)日：2006-01-03

    申请号：US10618220

    申请日：2003-07-11

    Applicant: Jingyi Bai ,  Weimin Li ,  William S. Budge

    Inventor： Jingyi Bai ,  Weimin Li ,  William S. Budge

    IPC: H01L21/76 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/31

    CPC classification number: H01L21/76224 ,  H01L21/76229

    Abstract: Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not bemused to interpret or limit the scope or meaning of the claims.

    Abstract translation: 提供了在半导体层中填充高纵横比沟槽的方法。 该方法利用HDP-CVD工艺用沟槽填充材料填充沟槽。 在这些方法中，气流和RF偏压被选择以提供对蚀刻比的高蚀刻，同时沟槽被部分填充。 然后选择气体流量和RF偏压，以在沟槽完全填充时提供低的沉积比。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交的理解是，不会被解释或限制权利要求的范围或含义。

    Semiconductor multilevel interconnect structure
    86.
    发明申请
    Semiconductor multilevel interconnect structure 审中-公开
    半导体多层互连结构

    公开(公告)号：US20050239002A1

    公开(公告)日：2005-10-27

    申请号：US11156709

    申请日：2005-06-21

    Applicant: Weimin Li

    Inventor： Weimin Li

    IPC: B32B9/04 ,  B32B9/06 ,  B32B15/04 ,  G03F7/00 ,  G03F7/11 ,  G03F7/20 ,  G03F7/36 ,  G03F7/40 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L21/31144 ,  H01L21/0331 ,  H01L21/31127 ,  H01L21/32139 ,  H01L21/76811

    Abstract: A method of fabricating a semiconductor multilevel interconnect structure employs a dual hardmask technique in a dual damascene process. The method includes using amorphous carbon as a first hardmask layer capable of being etched by a second etch process, and a second hardmask layer capable of being etched by a first etch process, as a dual hardmask. By virtue of the selective etch chemistry employed with the dual hardmask, the method affords flexibility unattainable with conventional processes. The via is never in contact with the photoresist, thus eliminating residual photoresist at the trench/via edge and the potential “poisoning” of the intermetal dielectric layer. Since trench/via imaging is completed before further etching, any patterning misalignments can be easily reworked. Because the amorphous carbon layer and the second hardmask layer are used as the dual hardmask, the photoresist can be made thinner and thus optimized for the best imaging performance.

    Abstract translation: 制造半导体多层互连结构的方法在双镶嵌工艺中采用双重硬掩模技术。 该方法包括使用无定形碳作为能够通过第二蚀刻工艺蚀刻的第一硬掩模层，以及能够通过第一蚀刻工艺被蚀刻的第二硬掩模层作为双重硬掩模。 凭借与双重硬掩模采用的选择性蚀刻化学方法，该方法提供了与常规工艺无法实现的灵活性。 通孔从不与光致抗蚀剂接触，从而消除沟槽/通孔边缘处的残余光致抗蚀剂以及金属间电介质层的潜在“中毒”。 由于在进一步蚀刻之前完成沟槽/通孔成像，因此可以容易地对任何图案化不对准进行重新加工。 由于无定形碳层和第二硬掩模层用作双重硬掩模，因此可以使光致抗蚀剂更薄，并因此优化以获得最佳成像性能。

    Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge
    87.
    发明授权
    Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge 有权
    沉积掺杂有P，B和Ge中的至少一种的包含二氧化硅的层的方法

    公开(公告)号：US06930058B2

    公开(公告)日：2005-08-16

    申请号：US10420246

    申请日：2003-04-21

    Applicant: Chris W. Hill ,  Weimin Li ,  Gurtej S. Sandhu

    Inventor： Chris W. Hill ,  Weimin Li ,  Gurtej S. Sandhu

    IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76 ,  H01L21/8238

    CPC classification number: C23C16/45523 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31625

    Abstract: A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two different time periods and under conditions effective to deposit a doped silicon dioxide layer on the substrate. The time periods and conditions are characterized by some period of time when one of said gaseous precursors comprising said dopant is flowed to the chamber in the substantial absence of flowing any of said oxidizer precursor. In one implementation, the time periods and conditions are effective to at least initially deposit a greater quantity of doped silicon dioxide within at least some gaps on the substrate as compared to any doped silicon dioxide deposited atop substrate structure which define said gaps.

    Abstract translation: 衬底位于沉积室内。 将至少两种气体前体进料到共同包含硅的室，包含氧和掺杂剂的氧化剂成为沉积的掺杂二氧化硅的一部分。 进料至少在两个不同的时间段内并且在有效沉积掺杂的二氧化硅层的条件下在基板上。 时间段和条件的特征在于一段时间，其中一种所述包含所述掺杂剂的气态前体在基本上不流动任何所述氧化剂前体的情况下流动到所述室。 在一个实施方案中，与沉积在限定所述间隙的衬底结构上的任何掺杂二氧化硅相比，时间段和条件有效地至少在衬底上的至少一些间隙内沉积更大量的掺杂二氧化硅。

    Passivation processes for use with metallization techniques
    88.
    发明申请
    Passivation processes for use with metallization techniques 有权
    钝化工艺用于金属化技术

    公开(公告)号：US20050032367A1

    公开(公告)日：2005-02-10

    申请号：US10931355

    申请日：2004-08-31

    Applicant: Weimin Li

    Inventor： Weimin Li

    IPC: H01L21/285 ,  H01L21/768 ,  H01L29/76 ,  H01L21/44 ,  H01L31/062

    CPC classification number: H01L21/76846 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76868 ,  H01L21/76876 ,  Y10S438/974

    Abstract: A method for passivating a substrate, such as a semiconductor substrate, that is to be “metallized,” or on which a metal film or structure is to be formed, includes exposing regions of the substrate that are to be metallized to hydrogen radicals or nitrogen radicals. The regions of the substrate that are treated in this fashion are coated or “stuffed.” Passivation of this type may be effected with a plasma that includes a gas such as argon, nitrogen, helium, or hydrogen, or a mixture of any of the foregoing, which will remove oxygen molecules from the surface to which metal adhesion is desired. The metal may then be formed thereon. Hydrogen radicals may also be used to passivate the surface of a substrate, such as a semiconductor substrate, from spontaneous fluorine etching. Such passivation is, of course, effected in a substantially fluorine free environment.

    Abstract translation: 将要被金属化或其上形成金属膜或结构的诸如半导体衬底的衬底钝化的方法包括将被金属化的衬底的区域暴露于氢自由基或氮 激进分子 以这种方式处理的基材的区域被涂覆或“填充”。 这种类型的钝化可以用等离子体来实现，该等离子体包括诸如氩，氮，氦或氢的气体，或者任何前述物质的混合物，其将从期望金属附着的表面除去氧分子。 然后可以在其上形成金属。 氢自由基也可用于从自发氟蚀刻钝化诸如半导体衬底的衬底的表面。 当然，这种钝化在基本上无氟的环境中实现。

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