公开(公告)号：US5572462A

公开(公告)日：1996-11-05

申请号：US510259

申请日：1995-08-02

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： G11C11/56

CPC分类号： G11C11/5692 ,  G11C11/56 ,  G11C7/1006

摘要： A multistate PROM and decompressor comprises a PROM array including a plurality of cells arranged to have a plurality of wordlines and a plurality of bitlines, where each cell is configured to have one of a plurality of threshold voltages (Vt0-Vtn). A Vt-detector is coupled to the PROM array and configured to receive a high voltage wordline (WLHV) signal that is ramped from a first voltage (e.g. 0V or ground) to a second voltage (e.g. Vtmax). The Vt-detector is configured to compare the WLHV signal to a plurality of predetermined thresholds and to output a detector word in response to the WLHV signal. An addressed memory cell is selected by a wordline select signal and a bitline select signal. A wordline selector is coupled to the PROM array and configured to receive the WLHV signal. The wordline selector communicates the WLHV signal to a selected wordline in response to the wordline select signal. A bitline selector is coupled to the PROM array and configured to select a selected bitline carrying a bitline signal in response to the bitline select signal. A decompressor is coupled to the Vt-detector and the bitline selector and is configured to receive the detector word and the bitline signal. When the WLHV signal voltage meets the addressed cell's voltage threshold, the addressed memory cell is turned on and the selected bitline signal is activated. Then, the detector word is latched into the decompressor and the data stored in the addressed memory cell is delivered to an output terminal. The first embodiment can be combined with a pump generator. A pump generator delivers a relatively high voltage to the WLHV signal input in order to permit a greater expanse among the operational voltage or current levels. This feature increases the range over which the selectable voltages operate. An advantage of this approach is that there is a greater chance of correct interpretation by the Vt-detector and decompressor.

摘要翻译： 多状态PROM和解压缩器包括PROM阵列，其包括被布置为具有多个字线和多个位线的多个单元，其中每个单元被配置为具有多个阈值电压（Vt0-Vtn）中的一个。 Vt检测器耦合到PROM阵列并且被配置为接收从第一电压（例如0V或接地）斜坡到第二电压（例如Vtmax）的高电压字线（WLHV）信号。 Vt检测器被配置为将WLHV信号与多个预定阈值进行比较，并且响应于WLHV信号输出检测器字。 寻址的存储单元由字线选择信号和位线选择信号选择。 字线选择器耦合到PROM阵列并被配置为接收WLHV信号。 字线选择器响应于字线选择信号将WLHV信号传送到所选择的字线。 位线选择器耦合到PROM阵列并且被配置为响应于位线选择信号来选择携带位线信号的选定位线。 解压缩器耦合到Vt检测器和位线选择器，并被配置为接收检测器字和位线信号。 当WLHV信号电压满足寻址单元的电压阈值时，寻址的存储单元导通，并且所选择的位线信号被激活。 然后，检测器字被锁存到解压缩器中，并且存储在寻址的存储单元中的数据被传送到输出端。 第一实施例可以与泵发生器组合。 泵发生器向WLHV信号输入端提供相对高的电压，以便允许在工作电压或电流水平之间更大的扩展。 该功能增加了可选电压工作的范围。 这种方法的一个优点是Vt检测器和解压缩器有更正确的解释机会。

公开(公告)号：US5314845A

公开(公告)日：1994-05-24

申请号：US474177

申请日：1990-02-02

申请人： Peter W. Lee ,  David N. Wang ,  Makoto Nagashima ,  Kazuto Fukuma ,  Tatsuya Sato

发明人： Peter W. Lee ,  David N. Wang ,  Makoto Nagashima ,  Kazuto Fukuma ,  Tatsuya Sato

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/532 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/463

CPC分类号： H01L21/02129 ,  C23C16/401 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02343 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76819 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002

摘要： A two step process is disclosed for forming a silicon oxide layer over a stepped surface of a semiconductor wafer while inhibiting the formation of voids in the oxide layer which comprises depositing a layer of an oxide of silicon over a stepped surface of a semiconductor wafer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3, and tetraethylorthosilicate as the gaseous source of silicon while maintaining the pressure in the CVD chamber within a range of from about 250 Torr to about 760 Torr and then depositing a second layer of oxide over the first layer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3 ; and tetraethylorthosilicate as the gaseous source of silicon while maintaining the CVD chamber at a lower pressure than during the first deposition step.

摘要翻译： 公开了一种用于在半导体晶片的阶梯表面上形成氧化硅层的两步法，同时抑制氧化物层中的空隙的形成，其包括在半导体晶片的台阶表面上沉积硅的氧化物层 CVD室通过将包含氧源的气体混合物（其一部分包含O 3）和原硅酸四乙酯作为气态硅流入气室，同时将CVD室中的压力保持在约250托至约760的范围内 然后通过流入室中在CVD室中的第一层上沉积第二层氧化物，气体混合物包含氧源，其一部分包含O 3; 和原硅酸四乙酯作为气态硅源，同时将CVD室保持在比在第一沉积步骤期间更低的压力。

公开(公告)号：US5309639A

公开(公告)日：1994-05-10

申请号：US979902

申请日：1992-11-23

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： B22F3/11 ,  B22F3/24 ,  B23H9/00 ,  B23P13/04 ,  F16C33/60 ,  F16C33/66 ,  B23P13/02 ,  F16C33/64

CPC分类号： F16C33/6648 ,  B22F3/1103 ,  B22F3/24 ,  B23H9/008 ,  B23P13/04 ,  F16C19/364 ,  F16C33/605 ,  Y10S384/902 ,  Y10T29/49639 ,  Y10T29/49689 ,  Y10T29/49702 ,  Y10T29/49707 ,  Y10T29/49996

摘要： A machine component has a wear surface along which excessive friction will develop unless the surface receives adequate lubrication. To provide lubrication for the wear surface in the absence of any other lubricating medium, the component is formed from powdered metal compacted to less than theoretical density so as to contain pores, and the pores hold oil. Even though the component is mechanically machined along its wear surface, the pores are nevertheless open at the wear surface to enable the entrapped oil to exude from the ring and lubricate that surface. During manufacture of the ring, the mechanical machining creates a Bielby layer at the wear surface, that is it smears the metal and closes the pores at that surface, but the Bielby layer is removed by electro-discharge machining This procedure erodes the Bielby layer with electrical arcs so that the pores at the wear surface are again exposed and open.

摘要翻译： 机器部件具有磨损表面，除非表面受到足够的润滑，否则磨损表面将产生过大的摩擦。 为了在不存在任何其它润滑介质的情况下为磨损表面提供润滑，组分由压粉成小于理论密度的粉末金属形成，以便容纳孔隙，并且孔保持油。 尽管组件沿其磨损表面机械加工，但孔仍然在磨损表面打开，以使夹带的油从环中渗出并润滑该表面。 在环的制造过程中，机械加工在磨损表面产生Bielby层，即涂抹金属并封闭该表面的孔，但是通过放电加工去除Bielby层。该过程会将Bielby层与 电弧，使得磨损表面处的孔再次暴露和打开。

公开(公告)号：US4571097A

公开(公告)日：1986-02-18

申请号：US694441

申请日：1985-01-24

申请人： Peter W. Lee ,  Gary E. Kreider ,  Ronald L. Widner

发明人： Peter W. Lee ,  Gary E. Kreider ,  Ronald L. Widner

IPC分类号： F16C19/36 ,  F16C33/60 ,  F16C33/66

CPC分类号： F16C33/667 ,  F16C19/364 ,  F16C33/605 ,  F16C33/6674 ,  F16C33/6681

摘要： A tapered roller bearing has a rib ring against which the large ends of the tapered rollers for the bearing bear to prevent those rollers from being expelled from the annular space between the tapered raceways. The rib ring includes a porous, yet rigid, core and a jacket which covers the exposed surfaces of the core, except along an abutment face at which the large end faces of the rollers contact the rib ring. Here the pores of the core are exposed. The core at one of its other faces has a groove and the jacket has a port that opens into the groove. Pressurized oil is directed through the port and into the groove, from which it flows through the pores of the core and emerges at the abutment surface where it reduces friction between the abutment surface and the roller end faces.

摘要翻译： 圆锥滚子轴承具有肋环，用于轴承的圆锥滚子的大端部能够抵靠该肋环，以防止这些辊从锥形滚道之间的环形空间排出。 肋环包括多孔但刚性的芯和覆盖芯的暴露表面的护套，除了沿着辊的大端面接触肋环的邻接面之外。 这里，核心的孔被暴露。 其另一个面上的芯具有凹槽，并且护套具有通向凹槽的开口。 加压油被引导通过端口并进入凹槽中，从而流过该芯的孔隙，并且出现在邻接表面处，从而减小邻接表面和辊端面之间的摩擦。

公开(公告)号：US08355287B2

公开(公告)日：2013-01-15

申请号：US12806848

申请日：2010-08-23

申请人： Fu-Chang Hsu ,  Peter W. Lee

发明人： Fu-Chang Hsu ,  Peter W. Lee

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0458 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C16/3477 ,  G11C2211/5621

摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.

摘要翻译： 用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。 然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法 晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。 擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

公开(公告)号：US07177190B2

公开(公告)日：2007-02-13

申请号：US11025822

申请日：2004-12-24

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/04

摘要： A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two and three transistor EEPROM cell. The nonvolatile memory cells use a large positive programming voltage (+18V) applied to the word lines or select gating lines for programming the memory cells and a large negative erasing voltage (−18V) applied to the word lines or select gating lines for erasing the memory cells. The NOR-type Flash nonvolatile memory array is used to store code of embedded processor programs or application programs for smart cards. The EEPROM array is preferably used to store byte alterable data and NAND-type Flash nonvolatile memory array is used to store personalized biometric data such as Iris, DNA, facial picture and finger prints.

摘要翻译： 组合EEPROM，NOR型闪存和NAND型闪存非易失性存储器包含存储单元，其中浮置晶体管形成NAND型闪存非易失性存储单元，形成NOR型闪存非易失性存储单元以及一个或两个选择晶体管 形成两个和三个晶体管EEPROM单元。 非易失性存储单元使用施加到字线的大的正编程电压（+ 18V）或选择用于编程存储器单元的选通线和施加到字线的大的负擦除电压（-18V）或选择用于擦除的行的选通线 记忆细胞 NOR型闪存非易失性存储器阵列用于存储智能卡的嵌入式处理器程序或应用程序的代码。 EEPROM阵列优选用于存储字节可变数据，并且NAND型闪存非易失性存储器阵列用于存储诸如虹膜，DNA，面部图像和指纹之类的个性化生物特征数据。

公开(公告)号：US6153540A

公开(公告)日：2000-11-28

申请号：US34850

申请日：1998-03-04

申请人： Ishing Lou ,  Cary Ching ,  Peter W. Lee ,  Rong Pan ,  Paul Gee ,  Francimar Campana

发明人： Ishing Lou ,  Cary Ching ,  Peter W. Lee ,  Rong Pan ,  Paul Gee ,  Francimar Campana

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/31

CPC分类号： H01L21/02129 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/31625

摘要： A method and apparatus for controlling the wet-etch rate and thickness uniformity of a dielectric layer, such as a phosphosilicate glass layer (PSG) layer. The method is based upon the discovery that the atmospheric pressure at which a PSG layer is deposited affects the wet-etch rate of the same, during a subsequent processing step, as well as the layer's thickness uniformity. As a result, the method of the present invention includes the step of pressurizing the atmospheric pressure of a semiconductor process chamber within a predetermined range after the substrate is deposited therein. Flowed into the deposition zone is a process gas comprising a silicon source, all oxygen source, and a phosphorous source; and maintaining the deposition zone at process conditions suitable for depositing a phosphosilicate glass layer on the substrate.

摘要翻译： 一种用于控制诸如磷硅酸盐玻璃层（PSG）层的介电层的湿蚀刻速率和厚度均匀性的方法和装置。 该方法基于以下发现：沉积PSG层的大气压力在随后的处理步骤期间影响其湿蚀刻速率以及层的厚度均匀性。 结果，本发明的方法包括在衬底沉积之后在预定范围内对半导体处理室的大气压进行加压的步骤。 流入沉积区的是包括硅源，全氧源和磷源的工艺气体; 以及将沉积区保持在适合于在基底上沉积磷硅酸盐玻璃层的工艺条件。

公开(公告)号：US6103601A

公开(公告)日：2000-08-15

申请号：US330247

申请日：1999-06-10

申请人： Peter W. Lee ,  Stuardo Robles ,  Anand Gupta ,  Virendra V. S. Rana ,  Amrita Verma

发明人： Peter W. Lee ,  Stuardo Robles ,  Anand Gupta ,  Virendra V. S. Rana ,  Amrita Verma

IPC分类号： H01L21/768 ,  C23C16/40 ,  C23C16/56 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L23/522 ,  H01L21/425 ,  H01L21/469

CPC分类号： H01L21/02131 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31629

摘要： A fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment step includes forming a thin, undoped silicate glass layer on top of the FSG layer, and in another embodiment, the stability of the FSG film is increased by a post-treatment plasma step.

摘要翻译： 描述了具有低介电常数的氟掺杂硅酸盐玻璃（FSG）层和形成这种绝缘层的方法。 FSG层通过后处理步骤进行处理，以使该层对氟原子的吸湿和除气有抵抗作用。 在一个实施方案中，后处理步骤包括在FSG层的顶部上形成薄的未掺杂的硅酸盐玻璃层，在另一个实施方案中，通过后处理等离子体步骤来增加FSG膜的稳定性。

公开(公告)号：US5953255A

公开(公告)日：1999-09-14

申请号：US998418

申请日：1997-12-24

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C11/40

CPC分类号： G11C16/16 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C2211/565

摘要： An array of MOS memory cells having functionally symmetrical drain and source regions may be programmed and/or erased using low voltage, e.g., less than about 7V. In a NAND-type array, UV-erasure increases threshold voltage Vt to erase memory cell contents, and low voltage-low current hot-hole injection ("HHI") decreases Vt to program the memory cells. For NOR-type arrays, HHI decreases Vt to erase memory cell contents and channel-hot-electron ("CHE") injection increases Vt to program cell contents. Erase and program potentials are low (

摘要翻译： 具有功能对称的漏极和源极区域的MOS存储器单元的阵列可以使用低电压（例如小于约7V）被编程和/或擦除。 在NAND型阵列中，UV擦除增加阈值电压Vt以擦除存储单元内容，而低电压 - 低电流热空穴注入（“HHI”）减小Vt以对存储单元进行编程。 对于NOR型阵列，HHI减小Vt以擦除存储单元内容，并且通道热电子（“CHE”）注入增加Vt以编程单元内容。 擦除和编程电位低（<7V），使得阵列可以在具有低压电路的公共IC上轻松制造。 由于HHI强烈收敛Vt，存储单元可能存储两个以上的数据值，这增加了单元存储密度。 电池对称性允许在电池耐久性变得太麻烦之前交换源的漏极，这种交换可以显着增加阵列的耐久寿命。 阵列可用作闪速存储器，如EPROM替换，或作为一次可编程存储器。

公开(公告)号：US4731570A

公开(公告)日：1988-03-15

申请号：US943213

申请日：1986-09-08

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： H02P25/08 ,  H02P8/00

CPC分类号： H02P25/0925

摘要： An electrical drive circuit for a variable-speed switched reluctance motor having a bifilar winding is provided. First, second, and third thyristor switches (5,7,10) each having respective firing circuits (6,8,11) are associated with the motor. A commutation capacitor device (9) is associated with one of the thyristor switches (5,7,10). A sensing means (33) determines the direction of current flow through the commutation capacitor device (9), and a control system (20) prevents the first and third thyristor switches (5,10) from conducting when the second thyristor switch (7) is conducting and prevents the first and second thyristor switches (5,7) from conducting when the third thyristor switch (10) is conducting.

摘要翻译： PCT No.PCT / US86 / 01846 Sec。 371日期1986年9月8日第 102（e）1986年9月8日PCT PCT。1986年9月8日PCT公布。 出版物WO87 / 01530 日期为1987年3月12日。提供具有双线绕组的变速开关磁阻电动机的电驱动电路。 每个具有各自的点火电路（6,8,11）的第一，第二和第三晶闸管开关（5,7,10）与电动机相关联。 换向电容器装置（9）与晶闸管开关（5,7,10）中的一个相关联。 感测装置（33）确定通过换向电容器装置（9）的电流的方向，并且当第二晶闸管开关（7）被控制时，控制系统（20）防止第一和第三晶闸管开关（5,10）导通， 正在导通并且防止当第三晶闸管开关（10）导通时第一和第二晶闸管开关（5,7）导通。