公开(公告)号：US06952051B1

公开(公告)日：2005-10-04

申请号：US09627649

申请日：2000-07-28

申请人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

发明人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L21/76837

摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

摘要翻译： 层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面 材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。 具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工 。 公开了形成层间电介质结构的各种方法。

公开(公告)号：US06940112B2

公开(公告)日：2005-09-06

申请号：US10234351

申请日：2002-08-30

申请人： Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

发明人： Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

IPC分类号： C23C16/40 ,  H01L21/02 ,  H01L21/76

CPC分类号： H01L28/60 ,  C23C16/40 ,  H01L28/55 ,  H01L28/90

摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

摘要翻译： 用于存储器件的电容器形成有用于底部电极的导电氧化物。 导电氧化物（RuO x S）在低温下作为非晶膜沉积。 结果，膜被共形沉积在三维折叠结构上。 此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。 沉积和抛光后，膜在非氧化环境中结晶。

公开(公告)号：US20050156240A1

公开(公告)日：2005-07-21

申请号：US11021651

申请日：2004-12-22

申请人： Gurtej Sandhu ,  Shubneesh Batra ,  Pierre Fazan

发明人： Gurtej Sandhu ,  Shubneesh Batra ,  Pierre Fazan

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/04 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8242

CPC分类号： H01L29/78678 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78672 ,  H01L29/78675

摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。

公开(公告)号：US20050151179A1

公开(公告)日：2005-07-14

申请号：US11003138

申请日：2004-12-03

申请人： Kunal Parekh ,  Gurtej Sandhu

发明人： Kunal Parekh ,  Gurtej Sandhu

IPC分类号： H01L21/28 ,  H01L21/30 ,  H01L21/60 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/3003 ,  H01L21/76832

摘要： A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

公开(公告)号：US20050147751A1

公开(公告)日：2005-07-07

申请号：US11075017

申请日：2005-03-08

申请人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri ,  Gurtej Sandhu ,  F. Gealy ,  Chris Carlson

发明人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri ,  Gurtej Sandhu ,  F. Gealy ,  Chris Carlson

IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C14/00 ,  C23C16/00

CPC分类号： C23C16/45519 ,  C23C16/4401 ,  C23C16/455

摘要： A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.

公开(公告)号：US20050121088A1

公开(公告)日：2005-06-09

申请号：US11034015

申请日：2005-01-11

申请人： Ross Dando ,  Gurtej Sandhu ,  Allen Mardian

发明人： Ross Dando ,  Gurtej Sandhu ,  Allen Mardian

IPC分类号： C23C16/44 ,  C23C16/452 ,  C23C16/455 ,  C30B25/10 ,  C30B25/14 ,  F16K11/072

CPC分类号： C30B25/14 ,  C23C16/452 ,  C23C16/45536 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/45561 ,  C30B25/105 ,  Y10S118/90 ,  Y10T137/86839 ,  Y10T137/86863

摘要： The invention includes chemical vapor deposition methods, including atomic layer deposition, and valve assemblies for use with a reactive precursor in semiconductor processing. In one implementation, a chemical vapor deposition method includes positioning a semiconductor substrate within a chemical vapor deposition chamber. A first deposition precursor is fed to a remote plasma generation chamber positioned upstream of the deposition chamber, and a plasma is generated therefrom within the remote chamber and effective to form a first active deposition precursor species. The first species is flowed to the deposition chamber. During the flowing, flow of at least some of the first species is diverted from entering the deposition chamber while feeding and maintaining plasma generation of the first deposition precursor within the remote chamber. At some point, diverting is ceased while feeding and maintaining plasma generation of the first deposition precursor within the remote chamber. Other aspects and implementations are contemplated.

公开(公告)号：US20050116064A1

公开(公告)日：2005-06-02

申请号：US11010534

申请日：2004-12-13

申请人： Cem Basceri ,  Gurtej Sandhu

发明人： Cem Basceri ,  Gurtej Sandhu

IPC分类号： C23C16/44 ,  C23C16/455 ,  F23D11/16

CPC分类号： C23C16/45574 ,  C23C16/45514 ,  C23C16/45544 ,  C23C16/45565

摘要： Reactors having gas distributors for depositing materials onto micro-device workpieces, systems that include such reactors, and methods for depositing materials onto micro-device workpieces are disclosed herein. In one embodiment, a reactor for depositing material on a micro-device workpiece includes a reaction chamber and a gas distributor in the reaction chamber. The gas distributor includes a first gas conduit having a first injector and a second gas conduit having a second injector. The first injector projects a first gas flow along a first vector and the second injector projects a second gas flow along a second vector that intersects the first vector in an external mixing zone facing the workpiece. In another embodiment, the mixing zone is an external mixing recess on a surface of the gas distributor that faces the workpiece.

公开(公告)号：US20050109271A1

公开(公告)日：2005-05-26

申请号：US10975714

申请日：2004-10-27

申请人： Gurtej Sandhu ,  Sujit Sharan

发明人： Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L21/02667 ,  C30B1/02 ,  C30B29/34 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/32053 ,  H01L29/7842

摘要： A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

摘要翻译： 形成结晶相材料的方法包括：a）在第一结晶相的结晶材料内部或在其中邻近的第一结晶相中提供应力诱导材料; 和b）在有效地将其转变成第二结晶相的条件下退火第一结晶相的结晶材料。 应力诱导材料优选在与第二结晶相退火期间在第一结晶相内诱导压应力，以降低所需的活化能以产生更致密的第二结晶相。 示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而用于提供层的应力诱导材料是Ge，W和Co 在压应力诱导材料设置在其上提供结晶相材料的晶片的相同侧上时，其被设置为具有小于第一相结晶材料的热膨胀系数。 在压应力诱导材料设置在提供结晶相材料的晶片的相对侧上的情况下，其被设置为具有大于第一相结晶材料的热膨胀系数。 具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSi x x。

公开(公告)号：US06888212B2

公开(公告)日：2005-05-03

申请号：US10254756

申请日：2002-09-24

申请人： Ravi Iyer ,  Gurtej Sandhu ,  Pai Pan

发明人： Ravi Iyer ,  Gurtej Sandhu ,  Pai Pan

IPC分类号： H01L21/762 ,  H01L21/208

CPC分类号： H01L21/76224

摘要： A method of forming isolation regions in a silicon substrate comprising the steps of forming a trench in the silicon substrate, filling the trench with a silanol polymer material then heating the silanol polymer material so that silicon dioxide is formed in the trench and thereby forms the isolation region. In the preferred embodiment, the silicon substrate is covered by a masking stack which is then etched to expose the underlying silicon substrate. The silicon substrate is then etched to form the trench and the silanol polymer material is deposited in the trench and fills the trench from the bottom up thereby avoiding divots and other defects. The silanol polymer grows faster on the silicon substrate than it does on the nitride. After the silanol polymer is reacted to form the silicon dioxide, CMP polishing is then used to remove the remaining masking stack and silicon dioxide above the surface of the silicon substrate.

摘要翻译： 一种在硅衬底中形成隔离区域的方法，包括以下步骤：在硅衬底中形成沟槽，用硅烷醇聚合物材料填充沟槽，然后加热硅烷醇聚合物材料，使得在沟槽中形成二氧化硅，从而形成隔离 地区。 在优选实施例中，硅衬底由掩模叠层覆盖，该掩模叠层然后被蚀刻以暴露下面的硅衬底。 然后蚀刻硅衬底以形成沟槽，并且硅烷醇聚合物材料沉积在沟槽中并从底部向上填充沟槽，从而避免纹理和其它缺陷。 在硅衬底上，硅烷醇聚合物比在氮化物上生长得更快。 在硅烷醇聚合物反应形成二氧化硅之后，然后使用CMP研磨去除硅衬底表面上剩余的掩模叠层和二氧化硅。

公开(公告)号：US06869877B2

公开(公告)日：2005-03-22

申请号：US10234581

申请日：2002-08-30

申请人： Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

发明人： Howard E. Rhodes ,  Mark Visokay ,  Tom Graettinger ,  Dan Gealy ,  Gurtej Sandhu ,  Cem Basceri ,  Steve Cummings

IPC分类号： C23C16/40 ,  H01L21/02 ,  H01L21/44

CPC分类号： H01L28/60 ,  C23C16/40 ,  H01L28/55 ,  H01L28/90

摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

摘要翻译： 用于存储器件的电容器形成有用于底部电极的导电氧化物。 导电氧化物（RuOx）在低温下作为非晶膜沉积。 结果，膜被共形沉积在三维折叠结构上。 此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。 沉积和抛光后，膜在非氧化环境中结晶。