公开(公告)号：US20120238091A1

公开(公告)日：2012-09-20

申请号：US13481550

申请日：2012-05-25

申请人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： H01L21/768

CPC分类号： H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.

摘要翻译： 本公开提供了通孔结构及其制造方法的各种实施例。 在一个实例中，用于形成通孔结构的方法包括在半导体衬底中形成通孔，其中通孔的通孔侧壁由半导体衬底限定; 在所述通孔侧壁上形成介电层; 从所述通孔侧壁的一部分去除所述介电层; 以及形成导电层以填充所述通孔，其中所述导电层设置在所述电介质层和所述通孔侧壁的所述部分之上。 在一个实例中，电介质层是氧化物层。

公开(公告)号：US08207595B2

公开(公告)日：2012-06-26

申请号：US12898408

申请日：2010-10-05

申请人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： H01L29/40

CPC分类号： H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.

摘要翻译： 半导体器件包括衬底晶片，覆盖衬底晶片的电介质层，电介质层中的图案化导体层和覆盖导体层的第一势垒层。 硅顶片结合到电介质层。 通孔通过顶部晶片和介电层的一部分形成到第一阻挡层。 侧壁电介质层沿通孔的内壁形成，与顶部晶片相邻，距离顶部晶片的上表面一定距离，形成侧壁电介质层的肩部。 在侧壁电介质层的内侧形成侧壁阻挡层，将通孔从第一阻挡层衬套到顶部晶片的上表面。 导电层填充通孔，并且在导电层，侧壁阻挡层和顶部晶片上形成顶部阻挡层。

公开(公告)号：US20120132921A1

公开(公告)日：2012-05-31

申请号：US12956145

申请日：2010-11-30

申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

IPC分类号： H01L29/20 ,  H01L21/20 ,  H01L21/18

CPC分类号： H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02658 ,  H01L29/66446 ,  H01L29/66522 ,  H01L33/007

摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有相对的第一和第二侧面的硅衬底。 第一和第二面中的至少一个包括硅（111）表面。 该方法包括在硅衬底的第一侧上形成高的热膨胀系数（CTE）层。 高CTE层的CTE大于硅的CTE。 该方法包括在硅衬底的第二侧上形成缓冲层。 缓冲层的CTE大于硅的CTE。 该方法包括在缓冲层上形成III-V族层。 III-V族层的CTE大于缓冲层的CTE。

公开(公告)号：US08178422B2

公开(公告)日：2012-05-15

申请号：US12415005

申请日：2009-03-31

申请人： Alex Hsu ,  Shih-Chi Fu ,  Feng-Jia Shiu ,  Chia-Shiung Tsai

发明人： Alex Hsu ,  Shih-Chi Fu ,  Feng-Jia Shiu ,  Chia-Shiung Tsai

IPC分类号： H01L21/76 ,  H01L21/00 ,  H01L23/544

CPC分类号： G03F9/7084 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/7088

摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有前侧和后侧的器件衬底，器件衬底具有第一折射率，在器件衬底的前侧上形成嵌入的靶，在嵌入的靶上形成反射层，形成介质 所述介质层具有小于所述第一折射率的第二折射率，并且从所述背面将辐射从所述介质层和所述器件基板突出以使得所述嵌入的靶被检测为半导体 处理。

公开(公告)号：US20120056305A1

公开(公告)日：2012-03-08

申请号：US12874362

申请日：2010-09-02

申请人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/66287 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

摘要： The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

摘要翻译： 本公开提供了一种双极结型晶体管（BJT）器件和用于制造BJT器件的方法。 在一个实施例中，BJT器件包括：具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构，间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度，顶部宽度基本上等于底部宽度。

公开(公告)号：US20110266511A1

公开(公告)日：2011-11-03

申请号：US12770344

申请日：2010-04-29

申请人： Ming-Huei Shen ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Ming-Huei Shen ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L45/00 ,  H01L21/20

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16

摘要： A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.

摘要翻译： 提供一种半导体器件，其包括形成在衬底上的底部电极接触件和形成在底部电极接触件上的电介质层。 该装置还包括形成在电介质层中的加热元件，其中加热元件设置在将电加热元件与电介质层分开的两个气隙之间，以及形成在加热元件上的相变元件，其中相变元件包括 基本无定形背景和活性区域，该活性区域能够改变无定形和结晶之间的相。 还提供了一种形成这种装置的方法。

公开(公告)号：US20110143514A1

公开(公告)日：2011-06-16

申请号：US12754451

申请日：2010-04-05

申请人： Jhon Jhy Liaw ,  Yu-Jen Wang ,  Chia-Shiung Tsai

发明人： Jhon Jhy Liaw ,  Yu-Jen Wang ,  Chia-Shiung Tsai

IPC分类号： H01L21/28

CPC分类号： H01L43/12 ,  B82Y10/00 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/08

摘要： Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

公开(公告)号：US20100151615A1

公开(公告)日：2010-06-17

申请号：US12710441

申请日：2010-02-23

申请人： Gwo-Yuh Shiau ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Shih-Chi Fu ,  Chia-Shiung Tsai

发明人： Gwo-Yuh Shiau ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Shih-Chi Fu ,  Chia-Shiung Tsai

IPC分类号： H01L31/18

CPC分类号： H01L27/14687 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14831

摘要： Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer.

摘要翻译： 提供了图像传感器装置及其制造方法。 图像传感器装置的示例性实施例包括支撑衬底。 在支撑衬底上形成钝化结构。 在钝化结构上形成互连结构。 第一半导体层形成在互连结构上，具有第一和第二表面，其中第一和第二表面是相对的表面。 至少一个感光装置从其第一表面形成在第一半导体层之上/之中。 滤色器层从其第二表面形成在第一半导体层上。 在滤色器层上形成至少一个微透镜。

公开(公告)号：US07723128B2

公开(公告)日：2010-05-25

申请号：US12032973

申请日：2008-02-18

申请人： Yung-Hung Wang ,  Yu-Jen Wang ,  Mark Juang ,  Chia-Shiung Tsai

发明人： Yung-Hung Wang ,  Yu-Jen Wang ,  Mark Juang ,  Chia-Shiung Tsai

IPC分类号： H01L21/00

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  H01L43/08 ,  H01L43/12

摘要： A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.

摘要翻译： 形成集成电路的方法包括形成磁隧道结（MTJ）层; 蚀刻MTJ层以形成MTJ电池; 以及在MTJ电池的侧壁上形成电介质覆盖层，其中形成电介质覆盖层的步骤是用蚀刻MTJ层的步骤进行的。

公开(公告)号：US07544982B2

公开(公告)日：2009-06-09

申请号：US11542064

申请日：2006-10-03

申请人： Chung-Yi Yu ,  Chia-Shiung Tsai ,  Shih-Chi Fu

发明人： Chung-Yi Yu ,  Chia-Shiung Tsai ,  Shih-Chi Fu

IPC分类号： H01L31/062

CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687

摘要： An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over the photosensor region. Preferably, barrier layers are located between the IMD layers. Preferably, each of the barrier layers at each level has a net thickness limited to 100 angstroms or less at locations over the photosensor region, except at locations where the IMD-level micro-lenses are located. The IMD-level micro-lenses and the etch stop layers preferably have a refractive index greater than that of the IMD layers. A cap layer is preferably formed on the metal lines, especially when the metal lines include copper. An upper-level micro-lens may be located on a level that is above the interconnection structure.

摘要翻译： 提供图像传感器装置。 衬底在其中和/或其上形成有光电传感器区域。 在衬底上形成互连结构，并且包括在金属间电介质（IMD）层中形成的金属线。 在光电传感器区域中的至少一个IMD层中形成至少一个IMD级微透镜。 优选地，阻挡层位于IMD层之间。 优选地，除了在IMD级微透镜所在的位置之外，每个级别的每个阻挡层的净厚度在光电传感器区域之外的位置处具有限制在100埃或更小的净厚度。 IMD级微透镜和蚀刻停止层优选具有大于IMD层的折射率的折射率。 优选在金属线上形成覆盖层，特别是当金属线包括铜时。 上级微透镜可以位于互连结构之上的层上。