公开(公告)号：US09271403B2

公开(公告)日：2016-02-23

申请号：US14165855

申请日：2014-01-28

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Hong Wan Ng

IPC: H05K3/30 ,  H01L23/13 ,  H01L23/498 ,  H05K3/10 ,  H05K3/34 ,  H01L23/31 ,  H01L23/00

CPC classification number: H05K3/303 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/06156 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H05K3/10 ,  H05K3/34 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract translation: 下面描述具有多层基板的半导体组件和相关制造方法的各种实施例。 在一个实施例中，用于承载半导体管芯的衬底包括第一路由级别，第二路由级别以及第一和第二路由级别之间的导电通路。 导电通孔具有接近第一路由级的第一端和靠近第二路由级的第二端。 第一路由级别包括端子和导体通孔的端子与第一端之间的第一迹线。 第二路由级别包括导电通孔的第二端和球场之间的第二迹线。 第一路由级别的终端和第二路由级别的球点都可以从基板的同一侧进行电连接。

公开(公告)号：US20150311186A1

公开(公告)日：2015-10-29

申请号：US14264699

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Hong Wan Ng

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/0665

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

Abstract translation: 本文公开了具有管芯支撑构件和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括封装衬底，附接到封装衬底的第一半导体管芯和附接到封装衬底的支撑构件。 支撑构件可以与第一半导体管芯分离，并且第二半导体管芯可以具有联接到支撑构件的一个区域和耦合到第一半导体管芯的另一个区域。

公开(公告)号：US20150311185A1

公开(公告)日：2015-10-29

申请号：US14264584

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

Abstract translation: 本文公开了具有支撑构件和相关系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括封装衬底，附接到封装衬底的第一半导体管芯，以及也附接到封装衬底的多个支撑构件。 多个支撑构件可以包括第一支撑构件和设置在第一半导体管芯的相对侧的第二支撑构件，并且第二半导体管芯可以联接到支撑构件，使得第二半导体管芯的至少一部分 在第一个半导体芯片上。

公开(公告)号：US12293992B2

公开(公告)日：2025-05-06

申请号：US18225369

申请日：2023-07-24

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

公开(公告)号：US12148736B2

公开(公告)日：2024-11-19

申请号：US17592065

申请日：2022-02-03

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

公开(公告)号：US20240304598A1

公开(公告)日：2024-09-12

申请号：US18424693

申请日：2024-01-26

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Dalson Ye ,  Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Ling Pan ,  See Hiong Leow

IPC: H01L25/065 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H10B80/00 ,  H01L2225/06506

Abstract: A microelectronic device includes a controller device, a first die vertically overlying the controller device, a second die vertically overlying the first die, and a wire. The first die includes a first pad horizontally separated from a horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance larger than the first distance. The wire contacts the first pad of the first die and the second pad of the second die. Memory device packages and electronic systems are also disclosed.

公开(公告)号：US12080616B2

公开(公告)日：2024-09-03

申请号：US17552217

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Suresh K. Upadhyayula ,  Yeow Chon Ong ,  Hong Wan Ng

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/295 ,  H01L23/562 ,  H01L25/0657 ,  H01L23/3121 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: The subject application relates to reinforced semiconductor device packaging and associated systems and methods. The device generally includes a substrate and one or more integrated circuit dies electrically coupled to the substrate with wire bonds. The device includes an encapsulant enclosing the one or more dies and the wire bonds. The package can include a reinforcing layer positioned on one or more surfaces of the encapsulant, a reinforcing wire extending through the encapsulant, or entrained reinforcing fiber portions positioned throughout the encapsulant. The reinforcing layer can be textile woven from synthetic or natural fibers, such as aramid, carbon, or glass. The package can be formed by disposing a reinforcing textile layer in a mold, placing a die and substrate in the mold with a liquid encapsulant, and hardening the liquid encapsulant to adhere the reinforcing textile layer, the encapsulant, the die, and the substrate together.

公开(公告)号：US20240128254A1

公开(公告)日：2024-04-18

申请号：US18394185

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

公开(公告)号：US20240074048A1

公开(公告)日：2024-02-29

申请号：US17894070

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Seng Kim Ye ,  See Hiong Leow

IPC: H05K1/11 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/111 ,  H01L24/16 ,  H01L25/0657 ,  H05K1/181 ,  H05K3/4644 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16237 ,  H01L2225/0652 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/10159 ,  H05K2201/10734

Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.

公开(公告)号：US20240071880A1

公开(公告)日：2024-02-29

申请号：US17897155

申请日：2022-08-27

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/16 ,  H01L24/16 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.