公开(公告)号：US20190115286A1

公开(公告)日：2019-04-18

申请号：US15787471

申请日：2017-10-18

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Eiichi Nakano

IPC: H01L23/498 ,  H01R12/77 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.

公开(公告)号：US20190067038A1

公开(公告)日：2019-02-28

申请号：US16123158

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  John F. Kaeding ,  Ashok Pachamuthu ,  Mark E. Tuttle

IPC: H01L21/56 ,  H01L23/31

Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.

公开(公告)号：US20240284590A1

公开(公告)日：2024-08-22

申请号：US18436892

申请日：2024-02-08

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  James M. Derderian ,  Walter L. Moden ,  Christopher Glancey

IPC: H05K1/02 ,  G01R31/309 ,  H05K3/28

CPC classification number: H05K1/0269 ,  G01R31/309 ,  H05K3/28

Abstract: Aspects of the present disclosure configure a processor to detect faults in a printed circuit board (PCB) solder mask using an optical waveguide. The processor directs an optical beam to an input of one or more optical waveguides embedded in a protective coating layer of a PCB, the protective coating layer being adjacent to one or more traces of the PCB. The processor measures a beam characteristic of the optical beam that is output by the one or more optical waveguides. The processor detects a disruption of the optical beam that is output by the one or more optical waveguides based on the beam characteristic. The processor detects a fault in the protective coating layer of the PCB based on detecting the disruption of the optical beam that is output by the one or more optical waveguides.

公开(公告)号：US11929349B2

公开(公告)日：2024-03-12

申请号：US17320116

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Ashok Pachamuthu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/49112 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

公开(公告)号：US11791315B2

公开(公告)日：2023-10-17

申请号：US17520568

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01L25/0657 ,  H01L23/3738 ,  H01L23/49877 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H05K1/0207 ,  H01L2224/16235 ,  H01L2224/17519 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06589 ,  H05K2201/066 ,  H05K2201/10159

Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors.

公开(公告)号：US11721742B2

公开(公告)日：2023-08-08

申请号：US17391920

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Thomas H. Kinsley ,  Randon K. Richards

IPC: H05K1/18 ,  H01L29/66 ,  H01L23/495 ,  H05K1/11 ,  H01L23/14

CPC classification number: H01L29/66015 ,  H01L23/145 ,  H01L23/49506 ,  H01L23/49513 ,  H05K1/117 ,  H05K1/181

Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

公开(公告)号：US11688658B2

公开(公告)日：2023-06-27

申请号：US17202542

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Shams U. Arifeen ,  Chan H. Yoo ,  Tracy N. Tennant

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/3114 ,  H01L23/3135 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device having a semiconductor die, a redistribution layer (RDL), and an encapsulant. The RDL layer can be formed on a first surface of the semiconductor die. The encapsulant can enclose a second surface and side surfaces of the semiconductor die. The encapsulant can enclose side portions of the RDL.

公开(公告)号：US20230187224A1

公开(公告)日：2023-06-15

申请号：US18106225

申请日：2023-02-06

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114

Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

公开(公告)号：US11664291B2

公开(公告)日：2023-05-30

申请号：US17115716

申请日：2020-12-08

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/36 ,  H01L23/42 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H05K7/20

CPC classification number: H01L23/36 ,  H01L23/42 ,  H01L23/49822 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K7/2039 ,  H01L2224/73204 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H05K2201/10378

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.

公开(公告)号：US20230084286A1

公开(公告)日：2023-03-16

申请号：US17991489

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Chan H. Yoo ,  Randon K. Richards ,  Timothy M. Hollis

IPC: G11C7/22 ,  G11C16/10 ,  G11C7/10

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.