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81.发明申请公开(公告)号：US20190130967A1
公开(公告)日：2019-05-02
申请号：US15799497
申请日：2017-10-31
CPC分类号： G11C11/5642 , G11C7/04 , G11C11/5635 , G11C16/22 , G11C16/26 , G11C16/349 , G11C2211/5644
摘要： Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
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公开(公告)号：US10263640B2
公开(公告)日：2019-04-16
申请号：US15478895
申请日：2017-04-04
发明人： Ivana Djurdjevic , Ara Patapoutian , Zheng Wang , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Ludovic Danjean , Erich F. Haratsch
IPC分类号： H03M13/11
摘要： Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
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公开(公告)号：US10153782B2
公开(公告)日：2018-12-11
申请号：US15198533
申请日：2016-06-30
发明人： Yu Cai , Yunxiang Wu , Erich F. Haratsch
摘要： A method of characterizing a distribution of a maximum number of errors that first cause uncorrectable error correction code failure for hard low density parity check codes includes selecting a low density parity check code, generating encoded data with the low density parity check code and writing the encoded data to a number of memory blocks, reading the encoded data from the number of memory blocks and determining any pages having a first uncorrectable error correction code failure, determining a number of raw bit errors for each page having a first uncorrectable error correction code failure, incrementing an error count value corresponding to each of the numbers of raw bit errors determined, and repeating the generating, reading, determining, and incrementing steps for a predetermined range of values of a predetermined reliability statistic of the memory blocks.
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公开(公告)号：US09990247B2
公开(公告)日：2018-06-05
申请号：US15407444
申请日：2017-01-17
IPC分类号： G06F11/07 , G06F11/10 , G11C29/52 , H03M13/45 , G11C7/10 , G11C11/56 , G11C16/10 , G11C27/00 , H03M13/25 , H03M13/29 , G11C16/26 , G06F11/32 , H03M13/11 , H03M13/15 , G06F3/06
CPC分类号： G06F11/0793 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/0727 , G06F11/0751 , G06F11/079 , G06F11/1068 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C27/005 , G11C29/52 , H03M13/1102 , H03M13/152 , H03M13/256 , H03M13/2906 , H03M13/45 , H03M13/458
摘要： An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.
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公开(公告)号：US09941901B2
公开(公告)日：2018-04-10
申请号：US15055006
申请日：2016-02-26
发明人： Zhengang Chen , Yunxiang Wu , Erich F. Haratsch
CPC分类号： H03M13/1111 , G06F11/1008 , G06F11/1012 , G06F11/1072 , G11C29/52 , H03M13/1154
摘要： Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.
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公开(公告)号：US20170322750A1
公开(公告)日：2017-11-09
申请号：US15659267
申请日：2017-07-25
发明人： Yu Cai , Yunxiang Wu , Ning Chen , Erich F. Haratsch , Zhengang Chen
IPC分类号： G06F3/06 , H03M13/37 , H03M13/11 , G11C29/52 , G11C16/08 , G06F12/02 , G06F11/10 , H03M13/00
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/7205 , G11C16/08 , G11C29/52 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/1128 , H03M13/3746 , H03M13/6505
摘要： Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.
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公开(公告)号：US20170287567A1
公开(公告)日：2017-10-05
申请号：US15626978
申请日：2017-06-19
发明人： Yu Cai , Yunxiang Wu , Erich F. Haratsch
CPC分类号： G11C16/3427 , G11C16/3418 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell.
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公开(公告)号：US20170148530A1
公开(公告)日：2017-05-25
申请号：US15423692
申请日：2017-02-03
发明人： Zhengang Chen , David Patmore , Yingji Ju , Erich F. Haratsch
CPC分类号： G11C29/42 , G06F3/064 , G06F11/00 , G11C7/10 , G11C11/5628 , G11C16/00 , G11C16/10 , G11C29/36 , G11C29/44 , G11C29/52 , H03M13/1108 , H04L1/00
摘要： An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
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公开(公告)号：US20170134053A1
公开(公告)日：2017-05-11
申请号：US15404619
申请日：2017-01-12
发明人： Yunxiang Wu , Yu Cai , Erich F. Haratsch
CPC分类号： H03M13/3927 , G06F8/65 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1076 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/3905 , H03M13/6325 , H03M13/6577 , H03M13/658 , H03M13/6588 , H03M13/6591
摘要： An apparatus includes a memory and a controller. The memory may be configured to store data. The memory generally comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to generate a set of converted log likelihood ratios by scaling a set of original log likelihood ratios using a selected scalar value, wherein the controller determines the selected scalar value by generating a plurality of sets of scaled log likelihood ratios by scaling the set of original log likelihood ratios with a plurality of corresponding scalar values, calculating a plurality of respective correlation coefficients each measuring a similarity of a respective set of scaled log likelihood ratios to the set of original log likelihood ratios, and selecting the scalar value corresponding to the set of scaled log likelihood ratios whose respective correlation coefficient is highest as the selected scalar value.
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公开(公告)号：US20170125114A1
公开(公告)日：2017-05-04
申请号：US15205654
申请日：2016-07-08
发明人： AbdelHakim S. Alhussien , Sundararajan Sankaranarayanan , Thuy Van Nguyen , Ludovic Danjean , Erich F. Haratsch
CPC分类号： G11C16/28 , G06F11/1012 , G11C11/5642 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/612 , H03M13/6325
摘要： Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page. (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.
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