利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

112 条记录 (耗时 0.018 秒)

    CELL-SPECIFIC REFERENCE GENERATION AND SENSING
    81.
    发明申请
    CELL-SPECIFIC REFERENCE GENERATION AND SENSING 有权

    公开(公告)号：US20170270990A1

    公开(公告)日：2017-09-21

    申请号：US15071490

    申请日：2016-03-16

    申请人： Micron Technology, Inc.

    发明人： Christopher John Kawamura ,  Scott James Derner

    IPC分类号： G11C11/22

    CPC分类号： G11C11/2273 ,  G11C7/14 ,  G11C11/221 ,  G11C11/2293

    摘要： Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

    FRAM cell with cross point access
    82.
    发明授权
    FRAM cell with cross point access 有权
    具有交叉点访问的FRAM单元

    公开(公告)号：US09236107B1

    公开(公告)日：2016-01-12

    申请号：US14324048

    申请日：2014-07-03

    申请人： Texas Instruments Incorporated

    发明人： Saim Ahmad Qidwai ,  Stephen Keith Heinrich-Barna ,  William Francis Kraus

    IPC分类号： G11C11/22 ,  G11C5/06 ,  G11C11/56 ,  G11C13/00

    CPC分类号： G11C11/221 ,  G11C5/06 ,  G11C11/22 ,  G11C11/2253 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C13/004

    摘要： A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.

    摘要翻译： 片上系统（SoC）可以具有阵列铁电位单元。 阵列可以包括组织成多个行和列的多个位单元。 一组字线被配置为使得多个字线中的一个字连接到一行位单元中的每个位单元。 提供了一组以列为单位的行列，其中每列位单元具有连接到位单元列中的每个位单元的多个板之一。 提供了一组位线，其中每列位单元具有连接到位单元列中的每个位单元的多个位线之一。 多路复用器可以用于允许一个平台驱动器，位线驱动器和感测放大器在多个板条和位线之间共享。

    FEEDBACK FOR MULTI-LEVEL SIGNALING IN A MEMORY DEVICE
    85.
    发明公开
    FEEDBACK FOR MULTI-LEVEL SIGNALING IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240256173A1

    公开(公告)日：2024-08-01

    申请号：US18403512

    申请日：2024-01-03

    申请人： Lodestar Licensing Group LLC

    发明人： M. Ataul Karim

    IPC分类号： G06F3/06 ,  G11C11/22 ,  G11C11/4076 ,  H03F3/45 ,  H03K3/356

    CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/2293 ,  G11C11/4076 ,  H03F3/45179 ,  H03K3/356113 ,  G11C11/221

    摘要： Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

    Deck-level shunting in a memory device
    86.
    发明授权
    Deck-level shunting in a memory device 有权

    公开(公告)号：US11978493B2

    公开(公告)日：2024-05-07

    申请号：US18084884

    申请日：2022-12-20

    申请人： Micron Technology, Inc.

    发明人： Daniele Vimercati

    IPC分类号： G11C11/22

    CPC分类号： G11C11/2255 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

    摘要： Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

    Digit Line Voltage Boosting Systems and Methods
    87.
    发明公开
    Digit Line Voltage Boosting Systems and Methods 审中-公开

    公开(公告)号：US20240071457A1

    公开(公告)日：2024-02-29

    申请号：US17896345

    申请日：2022-08-26

    申请人： Micron Technoiogy, Inc.

    发明人： Angelo Visconti ,  Andrea Locateiii

    IPC分类号： G11C11/22

    CPC分类号： G11C11/2295 ,  G11C11/2293 ,  G11C11/2297

    摘要： Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.

    Techniques for precharging a memory cell
    88.
    发明授权
    Techniques for precharging a memory cell 有权

    公开(公告)号：US11887689B2

    公开(公告)日：2024-01-30

    申请号：US17585307

    申请日：2022-01-26

    申请人： Micron Technology, Inc.

    发明人： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC分类号： G11C7/12 ,  G11C11/22

    CPC分类号： G11C7/12 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2273 ,  G11C11/2293

    摘要： Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

    Time-based access of a memory cell
    89.
    发明授权
    Time-based access of a memory cell 有权

    公开(公告)号：US11735244B2

    公开(公告)日：2023-08-22

    申请号：US17562557

    申请日：2021-12-27

    申请人： Micron Technology, Inc.

    发明人： Umberto Di Vincenzo

    IPC分类号： G11C11/22 ,  G11C11/00 ,  G11C11/56

    CPC分类号： G11C11/2273 ,  G11C11/005 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293 ,  G11C11/5657 ,  G11C11/22

    摘要： Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.