公开(公告)号：US20070145449A1

公开(公告)日：2007-06-28

申请号：US11643871

申请日：2006-12-22

Applicant: Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

Inventor： Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

IPC: H01L29/94

CPC classification number: H05K1/0231 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract translation: 一种电容器，其具有电容器，所述电容器包括：电容器主体，包括多个电介质层和设置在所述不同电介质层之间的内部电极层，其中所述电容器本体在所述电容器主体的至少一个侧面中， 从所述电容器主体的第一主面和位于与所述第一主面相反的一侧的第二主面中的至少一个在所述电容器本体的厚度方向上延伸的凹部。

公开(公告)号：US20070141800A1

公开(公告)日：2007-06-21

申请号：US11393910

申请日：2006-03-31

Applicant: Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki ,  Masatoshi Ishii

Inventor： Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki ,  Masatoshi Ishii

IPC: H01L21/20

CPC classification number: H01L23/5223 ,  H01G4/33 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L28/55 ,  H01L28/65 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/0179 ,  H05K2201/09481 ,  H05K2201/10712 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b lead from the first capacitor electrode 14 or the second capacitor electrode 18 and formed of a conducting barrier film which prevents the diffusion of hydrogen or water; and outside connection electrodes 34a, 34b for connecting to outside and connected to the leading-out electrodes 26a, 26b.

Abstract translation: 薄膜电容器包括形成在基底基板10上并包括第一电容器电极14，形成在第一电容器电极14上的电容器电介质膜16的电容器部分20和形成在电容器电介质膜16上的第二电容器电极18 ; 引出电极26a，26b从第一电容器电极14或第二电容器电极18引出，并由阻止氢或水扩散的导电阻挡膜形成; 以及用于连接到外部并连接到引出电极26a，26b的外部连接电极34a，34b。

公开(公告)号：US20070047175A1

公开(公告)日：2007-03-01

申请号：US11512247

申请日：2006-08-30

Applicant: Motohiko Sato ,  Kazuhiro Hayashi ,  Akifumi Tosa ,  Kenji Murakami ,  Tomohide Yamada ,  Motonobu Kurahashi

Inventor： Motohiko Sato ,  Kazuhiro Hayashi ,  Akifumi Tosa ,  Kenji Murakami ,  Tomohide Yamada ,  Motonobu Kurahashi

IPC: H01G4/005

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/435

Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.

Abstract translation: 一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。

公开(公告)号：US20070045815A1

公开(公告)日：2007-03-01

申请号：US11513249

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

IPC: H01L23/04

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/38 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.

Abstract translation: 布线板包括基板芯，陶瓷电容器和积层。 基板芯具有在芯主表面上开口的壳体开口部分。 陶瓷电容器容纳在壳体开口部分中并且取向为使得每个电容器的芯主表面和电容器主表面相同。 积层在其表面上的各个位置包括半导体集成电路元件安装区域。 在基板芯中，每个陶瓷电容器分别设置在对应于每个半导体集成电路元件安装区域的区域中。

公开(公告)号：US20060272853A1

公开(公告)日：2006-12-07

申请号：US11445288

申请日：2006-06-02

Applicant: Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

Inventor： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

IPC: H05K1/11 ,  H05K3/36

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wiring board comprising: a core board including a core body and a ceramic sub-core which is accommodated in a sub-core accommodation space that is a through-hole that communicates with major surfaces of the core body or a recess having an opening in a first major surface of the core body; and wiring laminates each formed by resin insulating layers and conductor layers laminated on each of major surfaces of the core board, wherein: a groove-filling portion which fills a gap between the core body and the ceramic sub-core is integral with a lowest resin insulating layer of the first-major-surface-side wiring laminate; and via conductors that are connected to respective conductor patterns formed on a first major surface of the ceramic sub-core penetrate through the lowest resin insulating layer.

Abstract translation: 一种布线板，包括：芯板，其包括芯体和陶瓷子芯，所述芯体容纳在与所述芯体的主表面连通的通孔的子芯容纳空间中，或者具有开口的凹部 核心体的第一个主要表面; 以及由层叠在芯板的各主表面上的树脂绝缘层和导体层形成的布线层叠体，其中，填充芯体与陶瓷副芯之间的间隙的沟槽填充部与最低树脂 第一主表面侧布线层叠体的绝缘层; 并且连接到形成在陶瓷子芯的第一主表面上的相应导体图案的通孔导体穿透最低树脂绝缘层。

公开(公告)号：US07002075B2

公开(公告)日：2006-02-21

申请号：US11126157

申请日：2005-05-11

Applicant: Rokuro Kambe ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

Inventor： Rokuro Kambe ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

IPC: H02G3/08

CPC classification number: H05K1/0231 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/50 ,  H01L27/016 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: An intermediate substrate includes a substrate core formed by a main core body portion constructed of a sheet of polymer material and having a subsidiary core accommodation portion formed therein. A ceramic subsidiary core portion, which is constructed of a ceramic sheet, is accommodated in the subsidiary core accommodation portion and is of a thickness matching that of the main core body portion. A thin film capacitor is formed on a first main surface side of a plate-like base of the core portion and includes first and second thin film electrodes separated from each other by a thin film dielectric layer so as to provide direct current isolation between the electrodes. First and second direct current isolated terminals of a first terminal array are electrically connected to the first and second thin film electrodes.

Abstract translation: 中间基板包括由主体芯体部分形成的基体芯部，所述主芯体部分由聚合物材料片构成并且具有形成在其中的副芯部容纳部分。 由陶瓷片构成的陶瓷副芯部被容纳在副芯容纳部中，其厚度与主芯体部的厚度一致。 在芯部的板状基体的第一主面侧形成薄膜电容器，并且包括通过薄膜电介质层彼此分离的第一和第二薄膜电极，以便在电极之间提供直流隔离 。 第一端子阵列的第一和第二直流隔离端子电连接到第一和第二薄膜电极。