公开(公告)号：US20140183738A1

公开(公告)日：2014-07-03

申请号：US13730184

申请日：2012-12-28

申请人： Christopher J. Jezewski ,  James S. Clarke ,  Tejaswi K. Indukuri ,  FLorian Gstrein ,  Daniel J. Zierath

发明人： Christopher J. Jezewski ,  James S. Clarke ,  Tejaswi K. Indukuri ,  FLorian Gstrein ,  Daniel J. Zierath

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L21/76841 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect comprising cobalt and method of forming a metal interconnect comprising cobalt are described. In an embodiment, a metal interconnect comprising cobalt includes a dielectric layer disposed on a substrate, an opening formed in the dielectric layer such that the substrate is exposed. The embodiment further includes a seed layer disposed over the substrate and a fill material comprising cobalt formed within the opening and on a surface of the seed layer.

摘要翻译： 描述了包括钴的金属互连和形成包含钴的金属互连的方法。 在一个实施例中，包括钴的金属互连包括设置在基板上的电介质层，形成在电介质层中的开口，使得基板被暴露。 该实施例还包括设置在基板上的种子层和在开口内和种子层的表面上形成的包含钴的填充材料。

公开(公告)号：US08441097B2

公开(公告)日：2013-05-14

申请号：US12646957

申请日：2009-12-23

申请人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

发明人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

IPC分类号： H01L21/02

CPC分类号： H01L28/90 ,  H01L27/0733

摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

摘要翻译： 描述形成具有凹陷电极的MIM电容器的存储器件的方法。 在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。 该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。 该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。 该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

公开(公告)号：US20110147888A1

公开(公告)日：2011-06-23

申请号：US12646957

申请日：2009-12-23

申请人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

发明人： Joseph M. Steigerwald ,  Nick Lindert ,  Steven J. Keating ,  Christopher J. Jezewski ,  Timothy E. Glassman

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/90 ,  H01L27/0733

摘要： Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

摘要翻译： 描述形成具有凹陷电极的MIM电容器的存储器件的方法。 在一个实施例中，形成具有凹陷电极的MIM电容器的方法包括形成由形成底部的下部和形成挖掘特征的侧壁的上部限定的挖掘特征。 该方法包括在特征中沉积下电极层，在下电极层上沉积电绝缘层，以及在电绝缘层上沉积上电极层以形成MIM电容器。 该方法包括去除MIM电容器的上部以暴露电极层的上表面，然后选择性地蚀刻电极层之一以使一个电极层凹陷。 该凹槽将电极彼此隔离并且减小了电极之间的电流泄漏路径的可能性。

公开(公告)号：US20200098657A1

公开(公告)日：2020-03-26

申请号：US16143001

申请日：2018-09-26

申请人： Arnab SEN GUPTA ,  Matthew METZ ,  Benjamin CHU-KUNG ,  Abhishek SHARMA ,  Van H. LE ,  Miriam R. RESHOTKO ,  Christopher J. JEZEWSKI ,  Ryan ARCH ,  Ande KITAMURA ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Lawrence WONG ,  Tahir GHANI

发明人： Arnab SEN GUPTA ,  Matthew METZ ,  Benjamin CHU-KUNG ,  Abhishek SHARMA ,  Van H. LE ,  Miriam R. RESHOTKO ,  Christopher J. JEZEWSKI ,  Ryan ARCH ,  Ande KITAMURA ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Lawrence WONG ,  Tahir GHANI

IPC分类号： H01L23/31 ,  H01L29/786 ,  H01L29/45 ,  H01L29/66 ,  H01L29/40

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20170148739A1

公开(公告)日：2017-05-25

申请号：US15129140

申请日：2014-06-16

申请人： Jeanette M. ROBERTS ,  Patricio E. ROMERO ,  Scott B. CLENDENNING ,  Christopher J. JEZEWSKI ,  Ramanan V. CHEBIAM

发明人： Jeanette M. ROBERTS ,  Patricio E. ROMERO ,  Scott B. CLENDENNING ,  Christopher J. JEZEWSKI ,  Ramanan V. CHEBIAM

IPC分类号： H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3215 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/3215 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/10734

摘要： Embodiments of the present disclosure describe a selective diffusion barrier between metals of an integrated circuit (IC) device and associated techniques and configurations. In one embodiment, an apparatus includes a dielectric material, a first interconnect structure comprising a first metal disposed in the dielectric material, a second interconnect structure comprising a second metal disposed in the dielectric material and electrically coupled with the first interconnect structure and a diffusion barrier disposed at an interface between the first interconnect structure and the second interconnect structure, wherein the first metal and the second metal have a different chemical composition, material of the diffusion barrier and the second metal have a different chemical composition and material of the diffusion barrier is not disposed directly between the second metal and the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US09129844B2

公开(公告)日：2015-09-08

申请号：US14319429

申请日：2014-06-30

申请人： Christopher J. Jezewski ,  Kevin P. O'Brien

发明人： Christopher J. Jezewski ,  Kevin P. O'Brien

IPC分类号： H01L49/02 ,  H01L21/48 ,  H01L23/64 ,  H01L23/522

CPC分类号： H01L28/10 ,  H01L21/4814 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。 例如，半导体管芯包括衬底。 集成电路设置在基板的有源表面上。 电感器耦合到集成电路。 电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。 绝缘层具有起伏的形貌。

公开(公告)号：US20150179515A1

公开(公告)日：2015-06-25

申请号：US14139363

申请日：2013-12-23

申请人： Christopher J. Jezewski ,  Jasmeet S. Chawla

发明人： Christopher J. Jezewski ,  Jasmeet S. Chawla

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/02126 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

公开(公告)号：US09054164B1

公开(公告)日：2015-06-09

申请号：US14139363

申请日：2013-12-23

申请人： Christopher J. Jezewski ,  Jasmeet S. Chawla

发明人： Christopher J. Jezewski ,  Jasmeet S. Chawla

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/02126 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

摘要翻译： 本发明的实施例描述了用于半导体器件的低电容互连结构以及用于制造这种器件的方法。 根据本发明的实施例，低电容互连结构包括层间电介质（ILD）。 第一和第二互连线以交替图案设置在ILD中。 第一互连线的顶表面可以在第二互连线的顶表面下方凹入。 第一互连线的凹槽中的增加减小相邻互连之间的线间电容。 另外的实施例包括利用不同的介电材料作为第一和第二互连线之上的蚀刻帽。 在蚀刻过程中，不同的材料可能具有彼此高的选择性。 因此，增加了对各个互连线的接触的对准预算。

公开(公告)号：US20140091467A1

公开(公告)日：2014-04-03

申请号：US13630724

申请日：2012-09-28

申请人： Christopher J. Jezewski ,  Alan M. Meyers ,  Kanwal Jit Singh ,  Tejaswik K. Indukuri ,  James S. Clarke ,  Florian Gstrein

发明人： Christopher J. Jezewski ,  Alan M. Meyers ,  Kanwal Jit Singh ,  Tejaswik K. Indukuri ,  James S. Clarke ,  Florian Gstrein

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76808 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.

摘要翻译： 本文描述了与形成阻挡壁，封盖或合金/化合物相关的技术结构，例如处理铜以形成合金或化合物，以减少电迁移（EM）并增强金属可靠性，随着线的长度增加而降低 集成电路。

公开(公告)号：US20140019716A1

公开(公告)日：2014-01-16

申请号：US13545910

申请日：2012-07-10

申请人： Christopher J. Jezewski

发明人： Christopher J. Jezewski

IPC分类号： H01L23/532 ,  G06F15/76 ,  G06F9/02 ,  H01L21/768

CPC分类号： H01L23/53252 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for forming a directly plateable diffusion barrier within an interconnect structure to prevent diffusion of interconnect fill metal into surrounding dielectric material and lower metal layers. The barrier can be used in back-end interconnect metallization processes and, in an embodiment, renders a seed layer unnecessary. In accordance with various example embodiments, the barrier can be implemented, for instance, as: (1) a single layer of ruthenium silicide (RuSix) or ruthenium silicide nitride (RuSixNy); (2) a bi-layer of Ru/RuSix, RuSix/Ru, Ru/RuSixNy, or RuSixNy/Ru; or (3) a tri-layer of Ru/RuSix/Ru or Ru/RuSixNy/Ru. In some embodiments, Si and/or N concentrations can be adjusted to alter the barrier's degree of diffusion protection, receptiveness to the fill metal, and/or electrical conductivity.

摘要翻译： 公开了用于在互连结构内形成直接平板化扩散阻挡层的技术，以防止互连填充金属扩散到周围的电介质材料和下层金属层。 阻挡层可以用于后端互连金属化工艺中，并且在一个实施例中使得不需要种子层。 根据各种示例性实施例，阻挡层可以例如如下实现：（1）单层钌硅化物（RuSix）或氮化钌氮化物（RuSixNy）; （2）Ru / RuSix，RuSix / Ru，Ru / RuSixNy或RuSixNy / Ru的双层; 或（3）Ru / RuSix / Ru或Ru / RuSixNy / Ru三层。 在一些实施方案中，可以调节Si和/或N浓度以改变屏障的扩散保护程度，对填充金属的接受性和/或导电性。