公开(公告)号：US20080303134A1

公开(公告)日：2008-12-11

申请号：US12156875

申请日：2008-06-05

申请人： Chun-Yuan Li ,  Hsiao-Jen Hung ,  Chin-Huang Chang ,  Jeng-Yuan Lai

发明人： Chun-Yuan Li ,  Hsiao-Jen Hung ,  Chin-Huang Chang ,  Jeng-Yuan Lai

IPC分类号： H01L23/52 ,  H01L21/02

CPC分类号： H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/0373 ,  H05K2201/09472 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer.

摘要翻译： 公开了一种半导体封装及其制造方法，其包括：提供载体板，在载体板上形成多个金属凸块，在载体板上形成金属层以封装金属凸块，具有至少一个 半导体芯片与金属层电连接，然后在载体板上形成密封剂以封装半导体芯片，接着去除载体板和金属凸块，以在密封剂的表面上相应地形成多个凹槽，其中底部和侧面 的沟槽被金属层覆盖以允许导电部件有效地定位在槽中并与金属层完全粘合。

公开(公告)号：US20090294959A1

公开(公告)日：2009-12-03

申请号：US12315787

申请日：2008-12-04

申请人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

发明人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/28 ,  H01L23/31

CPC分类号： H01L23/4334 ,  H01L21/486 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/81

摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

摘要翻译： 提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。 硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料 碰撞，切割晶片难度大。

公开(公告)号：US20090140440A1

公开(公告)日：2009-06-04

申请号：US12266830

申请日：2008-11-07

申请人： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

发明人： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.

摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上， 通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分 在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上 第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度并增加了布线粘合难度。

公开(公告)号：US20090057799A1

公开(公告)日：2009-03-05

申请号：US12229651

申请日：2008-08-26

申请人： Chang-Yueh Chan ,  Chih-Ming Huang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao

发明人： Chang-Yueh Chan ,  Chih-Ming Huang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L31/0203 ,  H01L31/02164 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

摘要： A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a part of the lead frame and to form a light-impervious encapsulant for encapsulating the transparent encapsulant. The transparent encapsulant has a light-pervious portion formed at a position corresponding to and above a sensor zone of the sensor chip. The light-pervious portion is exposed from the light-impervious encapsulant. Light may penetrate the light-pervious portion, without using an additional cover board, thereby reducing manufacturing steps and costs. The above arrangement avoids prior-art problems of poor reliability caused by a porous encapsulant and poor signal reception caused by interference of ambient light entering into a conventional chip only encapsulated by a transparent encapsulant.

摘要翻译： 提供一种传感器半导体器件及其制造方法。 至少一个传感器芯片被安装并电连接到引线框架。 依次执行第一和第二封装成型工艺以形成用于封装传感器芯片和引线框架的一部分的透明密封剂，并形成用于封装透明密封剂的不透光密封剂。 透明密封剂具有形成在对应于传感器芯片的传感器区域上方的位置处的透光部分。 透光部分从不透光的密封剂暴露出来。 光可以穿透透光部分，而不使用附加的盖板，从而减少制造步骤和成本。 上述布置避免了由多孔密封剂引起的可靠性差的现有技术问题，以及由仅通过透明密封剂封装的传统芯片的环境光的干扰引起的差信号接收。

公开(公告)号：US20080283982A1

公开(公告)日：2008-11-20

申请号：US12152802

申请日：2008-05-15

申请人： Chung-Lun Liu ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chang-Yueh Chan ,  Chih-Ming Huang

发明人： Chung-Lun Liu ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chang-Yueh Chan ,  Chih-Ming Huang

IPC分类号： H01L21/58 ,  H01L23/495

CPC分类号： H05K1/141 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3421 ,  H05K3/3436 ,  H05K2201/1034 ,  H05K2201/10659 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads. By the multi-chip semiconductor device and the method for fabricating the same as proposed in the present invention, problems like poor reliability caused by stress induced by several types of materials in a semiconductor package into which a substrate and leads are integrated, moisture absorption by an encapsulated substrate, and cracks developed as a result of moisture absorption by the substrate can be avoided.

摘要翻译： 本发明提出一种具有引线的多芯片半导体器件及其制造方法。 该方法包括以下步骤：提供具有设置在其表面上的多个连接焊盘的基板; 将多个半导体芯片安装在所述基板的表面上，并且将所述半导体芯片电连接到所述基板的表面; 在衬底上形成密封剂以封装半导体芯片并暴露连接焊盘以形成封装单元; 并且提供具有多个引线的引线框架，并且将从封装单元暴露的连接焊盘电连接到引线框架的引线以形成具有引线的多芯片半导体器件，从而形成具有引线的多芯片半导体器件 。 通过本发明中提出的多芯片半导体器件及其制造方法，由半导体封装中由几种材料引起的应力引起的可靠性差的问题，其中衬底和引线被集成到其中，由于 可以避免被封装的基材和由于基材吸湿而显影的裂纹。

公开(公告)号：US20070164411A1

公开(公告)日：2007-07-19

申请号：US11603687

申请日：2006-11-21

申请人： Chien-Ping Huang ,  Chin-Huang Chang

发明人： Chien-Ping Huang ,  Chin-Huang Chang

IPC分类号： H01L23/02

CPC分类号： H01L23/49811 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor chip having an active surface, a inactive surface, and a plurality of bond pads formed on the active surface; coupling one or more substrates to the active surface in such a way that the bond pads are exposed through one or more openings in the one or more substrates and/or gaps between the substrates to electrically connect the bond pads to the substrate; attaching and electrically connecting the semiconductor chip to a leadframe having a plurality of leads; and encapsulating the semiconductor chip, the substrate, and the leadframe with an encapsulant, with at least bottom surfaces of the leads of the leadframe being exposed from the encapsulant. An indented structure is therefore formed on the bottom surface of an inner portion of each of the leads of the leadframe.

摘要翻译： 提供半导体封装结构及其制造方法。 制造方法包括提供具有活性表面，非活性表面和形成在活性表面上的多个接合焊盘的半导体芯片; 将一个或多个衬底耦合到有源表面，使得接合焊盘通过衬底中的一个或多个衬底和/或间隙中的一个或多个开口暴露以将接合焊盘电连接到衬底; 将所述半导体芯片附接并电连接到具有多个引线的引线框架; 以及用密封剂封装半导体芯片，衬底和引线框架，至少引线框架的引线的底表面从密封剂露出。 因此，在引线框架的每个引线的内部的底表面上形成凹陷结构。

公开(公告)号：US08304891B2

公开(公告)日：2012-11-06

申请号：US12315787

申请日：2008-12-04

申请人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

发明人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

IPC分类号： H01L23/28 ,  H01L23/31 ,  H01L23/52 ,  H01L23/00

CPC分类号： H01L23/4334 ,  H01L21/486 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/81

摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

摘要翻译： 提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。 硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料 碰撞，切割晶片难度大。

公开(公告)号：US07981729B2

公开(公告)日：2011-07-19

申请号：US12818701

申请日：2010-06-18

申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/60

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

公开(公告)号：US20080230913A1

公开(公告)日：2008-09-25

申请号：US12077223

申请日：2008-03-18

申请人： Chien-Ping Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Chun-Chi Ke

发明人： Chien-Ping Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Chun-Chi Ke

IPC分类号： H01L23/488 ,  H01L21/304

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/05001 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices. Thereby, the first and second metal layers formed on the active surface and the non-active surface of the semiconductor device can be stacked and connected to constitute a multi-die stack structure, thereby increasing integration without increasing the area of the stacked dies. Further, the problems known in the prior art of poor electrical connection, complicated manufacturing process and increased cost as a result of using wire bonding and TSV can be avoided.

摘要翻译： 本发明提供了一种可堆叠半导体器件及其制造方法，包括提供具有安装在其上的多个管芯的晶片，晶粒和晶片两者分别具有相互相对的有源表面和非有效表面，其中每个管芯具有 形成在其有效表面上的多个焊盘和形成在相邻焊盘之间的槽，以在其中形成电连接到焊盘的第一金属层; 随后使所述晶片的非活性表面变薄到所述凹槽所在的位置以暴露出所述第一金属层，以及在所述晶片的非活性表面上形成用于与所述第一金属层电连接的第二金属层; 以及分离所述管芯以形成多个可堆叠的半导体器件。 由此，形成在半导体器件的有源表面和非有源表面上的第一和第二金属层可以被堆叠和连接以构成多管芯堆叠结构，从而增加集成度而不增加堆叠管芯的面积。 此外，可以避免由于使用引线接合和TSV而导致的不良电连接，复杂的制造工艺和增加的成本的现有技术中已知的问题。

公开(公告)号：US20070108571A1

公开(公告)日：2007-05-17

申请号：US11649144

申请日：2007-01-02

申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chung-Lun Liu

发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chung-Lun Liu

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49575 ,  H01L23/3135 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

摘要翻译： 提出了一种具有堆叠芯片的半导体封装及其制造方法。 半导体封装包括具有多个引线和支撑延伸部的引线框架; 至少一个具有活性表面的预制包装和连接到引线框架的支撑延伸部的非活性表面; 至少一个芯片安装在所述预制包装的有效表面上; 用于将引线框架，预成型封装和芯片电连接的多个接合线; 以及用于封装预制包装，芯片，接合线和引线框架的一部分的密封剂。 预制包装的活性表面用于承载芯片，并且可以用作跳线，以便解决多芯片模块的已知的良好的裸片（KGD）问题。