公开(公告)号：US20130147062A1

公开(公告)日：2013-06-13

申请号：US13567046

申请日：2012-08-04

Applicant: Hee-Jin LEE ,  Woo-Dong LEE

Inventor： Hee-Jin LEE ,  Woo-Dong LEE

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.

Abstract translation: 多芯片封装可以包括封装衬底，第一半导体芯片，第二半导体芯片和支撑构件。 第一半导体芯片可以布置在封装衬底的上表面上。 第一半导体芯片可以与封装衬底电连接。 第二半导体芯片可以布置在第一半导体芯片的上表面上。 第二半导体芯片可以与第一半导体芯片电连接。 第二半导体芯片可以具有突出超过第一半导体芯片的侧表面的区域的突起。 支撑构件可以插入在第二半导体芯片的突起与封装基板之间，以防止突起的偏转。 因此，突起可能不会偏转。

公开(公告)号：US20080099909A1

公开(公告)日：2008-05-01

申请号：US11927457

申请日：2007-10-29

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01L23/34 ,  H01L21/58

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and a coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并密封; 形成在冷却通孔圆周上的微孔; 以及填充冷却通孔内部的冷却剂。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20100181887A1

公开(公告)日：2010-07-22

申请号：US12691156

申请日：2010-01-21

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01J1/02

CPC classification number: H01L33/647 ,  G02B6/0023 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/01066 ,  H01L2924/00014

Abstract: A light emitting device with improved heat dissipation is provided. The light emitting device includes a first lead frame, a second lead frame, a light emitting element and a housing. The first lead frame includes a light emitting element mounting portion, a first heat dissipation portion extending from the light emitting element mounting portion in a first direction, and second and third heat dissipation portions extending from the light emitting element mounting portion in a second direction opposite to the first direction. The second lead frame extends in the second direction and is disposed between and spaced apart from the second and third heat dissipation portions. The light emitting element is mounted on the light emitting element mounting portion and is electrically coupled to the first and second lead frames. The housing encapsulates the first and second lead frames. The second and third heat dissipation portions have a first width and the second lead frame has a second width the same as or different from the first width.

Abstract translation: 提供了具有改善的散热的发光装置。 发光器件包括第一引线框架，第二引线框架，发光元件和壳体。 第一引线框架包括发光元件安装部分，从第一方向从发光元件安装部分延伸的第一散热部分和从发光元件安装部分沿相反的第二方向延伸的第二和第三散热部分 到第一个方向。 第二引线框架沿第二方向延伸并且设置在第二和第三散热部分之间并与第二和第三散热部分间隔开。 发光元件安装在发光元件安装部分上并且电耦合到第一引线框架和第二引线框架。 壳体封装第一和第二引线框架。 第二和第三散热部分具有第一宽度，第二引线框架具有与第一宽度相同或不同的第二宽度。

公开(公告)号：US20070252271A1

公开(公告)日：2007-11-01

申请号：US11740821

申请日：2007-04-26

Applicant: Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

IPC: H01L23/34

CPC classification number: H01L25/16 ,  G11C5/04 ,  H01L21/563 ,  H01L25/0655 ,  H01L2224/73203 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10159 ,  Y02P70/611

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract translation: 提供了一种半导体存储器模块，其允许形成在模块基板和安装在模块基板上的存储芯片之间的填充构件完全填充模块基板和存储器芯片之间的空间。 根据本发明的实施例，半导体存储器模块包括具有安装在基板上的至少一个存储芯片的模块基板，使得其边缘对于将模块基板平分的主轴和短轴倾斜。 倾斜方向允许在基板上形成的存储芯片之间的开口改善，使得填充构件可以适当地形成在模块基板和存储芯片之间，以防止填充构件未形成的空隙。

公开(公告)号：US20120001348A1

公开(公告)日：2012-01-05

申请号：US13235850

申请日：2011-09-19

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01L23/46

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并被密封; 形成在冷却通孔圆周上的微孔; 并且冷却剂填充在冷却通孔的内部。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20070252257A1

公开(公告)日：2007-11-01

申请号：US11741623

申请日：2007-04-27

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE ,  Hae-Hyung LEE ,  Sun-Won KANG

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE ,  Hae-Hyung LEE ,  Sun-Won KANG

IPC: H01L23/02

CPC classification number: H01L23/3675 ,  H01L23/36 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a semiconductor package structure includes a heat dissipative element connected to an internal circuit. The semiconductor package includes a semiconductor chip, an interconnection substrate, and a heat dissipative element. The semiconductor chip includes an internal circuit and inner pads that connect the internal circuit. The interconnection substrate is disposed below the semiconductor chip and includes input/output terminals. At least one of the inner pads is electrically connected to at least one of the input/output terminals. The heat dissipative element is disposed on the semiconductor chip and is electrically connected to at least one of the inner pads.

Abstract translation: 在一个实施例中，半导体封装结构包括连接到内部电路的散热元件。 半导体封装包括半导体芯片，互连衬底和散热元件。 半导体芯片包括连接内部电路的内部电路和内部焊盘。 互连基板设置在半导体芯片的下方并且包括输入/​​输出端子。 内部焊盘中的至少一个电连接到至少一个输入/输出端子。 散热元件设置在半导体芯片上并与至少一个内部焊盘电连接。

公开(公告)号：US20120045871A1

公开(公告)日：2012-02-23

申请号：US13210607

申请日：2011-08-16

Applicant: Hee-Jin LEE ,  Joong-Hyun Baek

Inventor： Hee-Jin LEE ,  Joong-Hyun Baek

IPC: H01L21/56

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/0615 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48647 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.

Abstract translation: 提供半导体芯片，半导体模块，电子系统的半导体封装及其制造方法。 该方法包括将半导体芯片安装在封装基板上，在半导体芯片上形成模制构件，形成穿过模制构件的通孔以暴露半导体芯片的顶表面的一部分，通孔布置成格子状 并且在通孔中通过塞子形成热传导。

公开(公告)号：US20100038769A1

公开(公告)日：2010-02-18

申请号：US12581920

申请日：2009-10-20

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01L25/065

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并密封; 形成在冷却通孔圆周上的微孔; 并且冷却剂填充在冷却通孔的内部。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20070126114A1

公开(公告)日：2007-06-07

申请号：US11562894

申请日：2006-11-22

Applicant: Hee-Jin LEE ,  Sun-Won KANG ,  Hae-Hyung LEE

Inventor： Hee-Jin LEE ,  Sun-Won KANG ,  Hae-Hyung LEE

IPC: H01L23/34 ,  H01L21/00

CPC classification number: H01L23/367 ,  H01L23/3677 ,  H01L2224/16 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: In one embodiment, a heat-dissipating member includes a heat-dissipating body, a heat-transferring body and an attaching member. The heat-dissipating body externally dissipates heat originating in a heat source. The heat-transferring member is interposable between the heat-dissipating body and the heat source. The attaching member is placed on a surface of the heat-dissipating body and corresponds to the heat-transferring body so as to couple the heat-transferring member to the heat-dissipating body. Thus, heat generated from the heat source, such as a semiconductor element, rapidly dissipates through the heat-transferring member and externally through the heat-dissipating body.

Abstract translation: 在一个实施例中，散热构件包括散热体，传热体和连接构件。 散热体外部散发源自热源的热量。 传热部件与散热体和热源之间可以相互嵌合。 安装构件放置在散热体的表面上并对应于传热体，以将传热构件耦合到散热体。 因此，从诸如半导体元件的热源产生的热量通过传热构件快速耗散并且在外部通过散热体散发。