公开(公告)号：US09911679B2

公开(公告)日：2018-03-06

申请号：US15425614

申请日：2017-02-06

Applicant: Infineon Techonologies Americas Corp.

Inventor： Eung San Cho

IPC: H01L23/367 ,  H05K1/18 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01F27/24 ,  H01F1/03

CPC classification number: H01L23/3675 ,  H01F1/0306 ,  H01F27/24 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/645 ,  H01L24/31 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/41173 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102 ,  H05K1/0209 ,  H05K1/165 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K2201/1003 ,  H05K2201/10166 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

公开(公告)号：US09620475B2

公开(公告)日：2017-04-11

申请号：US14546854

申请日：2014-11-18

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho

IPC: H01L29/15 ,  H01L23/00 ,  H01L23/433 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L24/73 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48245 ,  H01L2224/73213 ,  H01L2224/73215 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83191 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84424 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/92 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2924/00012

Abstract: In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.

公开(公告)号：US09443760B2

公开(公告)日：2016-09-13

申请号：US14543557

申请日：2014-11-17

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/13 ,  H01L23/433 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L25/07 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

Abstract translation: 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片，其中电互连具有接触夹和电沉积导体中的至少一个。

公开(公告)号：US09245832B2

公开(公告)日：2016-01-26

申请号：US14512368

申请日：2014-10-10

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akane Hasegawa ,  Kenji Okamoto

IPC: H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/495 ,  H01L23/433 ,  H01L23/373 ,  H01L23/36 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/40249 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48249 ,  H01L2224/48472 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83065 ,  H01L2224/83801 ,  H01L2224/84447 ,  H01L2224/85205 ,  H01L2224/85447 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/40247 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor module includes: a metal block; an insulation layer for heat radiation formed by directly depositing a ceramic material on at least a first surface of the metal block; an insulation layer for a relay electrode formed by directly depositing a ceramic material on a part of a second surface 1b of the metal block; a relay electrode formed by depositing a metal material on the upper surface of the insulation layer for the relay electrode; a circuit element bonded with the second surface of the metal block by solder; and an external lead terminal, wherein a bonding wire or a lead frame from the circuit element is bonded with the relay electrode, and the relay electrode and the external lead terminal are connected.

Abstract translation: 半导体模块包括：金属块; 用于通过在所述金属块的至少第一表面上直接沉积陶瓷材料形成的用于热辐射的绝缘层; 用于通过在金属块的第二表面1b的一部分上直接沉积陶瓷材料形成的用于继电器电极的绝缘层; 中继电极，其通过在用于所述中继电极的所述绝缘层的上表面上沉积金属材料而形成; 通过焊料与金属块的第二表面接合的电路元件; 以及外部引线端子，其中来自电路元件的接合线或引线框架与中继电极接合，并且继电器电极和外部引线端子被连接。

公开(公告)号：US20150162303A1

公开(公告)日：2015-06-11

申请号：US14546854

申请日：2014-11-18

Applicant: International Rectifier Corporation

Inventor： Eung San Cho

IPC: H01L23/00 ,  H01L27/06 ,  H01L23/34 ,  H01L27/088

CPC classification number: H01L24/73 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48245 ,  H01L2224/73213 ,  H01L2224/73215 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83191 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84424 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/92 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2924/00012

Abstract: In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.

Abstract translation: 在一个实施方式中，公开了一种制造功率半导体封装的方法。 该方法包括提供包括与连接条保持在一起的多个功率模块的导电载体阵列，其中多个功率模块中的每一个包括控制晶体管，同步晶体管和驱动器IC。 该方法还包括在导电载体阵列上覆盖散热器阵列，散热器阵列包括多个功率电极散热器，使得多个功率电极散热器中的每一个在每个功率中将同步晶体管的漏极耦合到控制晶体管的源极 模块。

公开(公告)号：US20150076570A1

公开(公告)日：2015-03-19

申请号：US14127187

申请日：2013-05-27

Applicant: NSK LTD.

Inventor： Takashi Sunaga ,  Noboru Kaneko ,  Osamu Miyoshi

IPC: H01L23/00 ,  H01L29/78

CPC classification number: H01L24/43 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/77 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L29/78 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/35847 ,  H01L2224/3701 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/4112 ,  H01L2224/41175 ,  H01L2224/43848 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/494 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/75272 ,  H01L2224/77272 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/85 ,  H01L2224/85815 ,  H01L2224/9221 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/1031 ,  H05K2201/10409 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/33 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/48227

Abstract: There is provided a semiconductor module and a method for manufacturing the same which make it possible to joint the electrode of the bare-chip transistor and the wiring pattern on the substrate by solder mounting operation, in the same process of solder mounting operation for mounting the bare-chip transistor or other surface mounting devices on the wiring patterns on the substrate. A semiconductor module includes: a plurality of wiring patterns formed on an insulating layer; a bare-chip transistor mounted on one wiring pattern out of the plurality of wiring patterns via a solder; and a copper connector constituted of a copper plate for jointing an electrode formed on a top surface of the bare-chip transistor and another wiring pattern out of the plurality of wiring patterns via a solder.

Abstract translation: 提供了一种半导体模块及其制造方法，其可以通过焊接安装操作将裸芯片晶体管的电极和布线图案与基板上的布线图案相连接，在相同的焊接安装操作过程中， 裸芯片晶体管或其他表面安装器件在基板上的布线图案上。 半导体模块包括：形成在绝缘层上的多个布线图案; 通过焊料在多个布线图案中安装在一个布线图案上的裸芯片晶体管; 以及铜连接器，其由用于通过焊料将形成在裸芯片晶体管的顶表面上的电极和多个布线图案中的另一布线图案连接的铜板构成。

公开(公告)号：US20130256856A1

公开(公告)日：2013-10-03

申请号：US13431125

申请日：2012-03-27

Applicant: Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

Inventor： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

公开(公告)号：US09837380B2

公开(公告)日：2017-12-05

申请号：US14165720

申请日：2014-01-28

Applicant: Infineon Technologies Austria AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01R4/00 ,  H01L25/07 ,  H01L23/433 ,  H01L23/495

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/48 ,  H01L24/70 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/89 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05554 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37026 ,  H01L2224/3719 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83143 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/84143 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/84825 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/84855 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/14253 ,  H01L2924/181 ,  H01R4/00 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2224/84

Abstract: A semiconductor device includes a device carrier, a first semiconductor chip mounted on the device carrier and a second semiconductor chip mounted on the device carrier. Further, the semiconductor device includes a first contact clip bonded to a first electrode of the first semiconductor chip, a second contact clip bonded to a first electrode of the second semiconductor chip and an insulating connector configured to hold the first contact clip and the second contact clip together.

公开(公告)号：US09673118B2

公开(公告)日：2017-06-06

申请号：US15038590

申请日：2014-07-31

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Masaki Taya

IPC: H01L23/02 ,  H01L23/053 ,  H01L25/07 ,  H01L25/18 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/535 ,  H01L23/24 ,  H01L23/00

CPC classification number: H01L23/053 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3142 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/535 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/35847 ,  H01L2224/37005 ,  H01L2224/37011 ,  H01L2224/37012 ,  H01L2224/37032 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/4046 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48245 ,  H01L2224/73263 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84205 ,  H01L2224/84447 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/2076

Abstract: A power module providing an improved manufacture yield and having an ensured stable joint strength and accordingly improved reliability is provided. The power module includes: a base portion having one surface on which an electrode portion is formed; a conductor portion disposed to face the one surface of the base portion on which the electrode portion is formed, for making electrical connection with the outside; and an interconnect portion connected to the electrode portion formed on the one surface of the base portion and to the surface of the conductor portion facing the one surface of the base portion for electrically connecting the electrode portion to the conductor portion.

公开(公告)号：US20170148705A1

公开(公告)日：2017-05-25

申请号：US15425614

申请日：2017-02-06

Applicant: Infineon Techonologies Americas Corp.

Inventor： Eung San Cho

IPC: H01L23/367 ,  H01L23/00 ,  H01F1/03 ,  H01L23/498 ,  H01F27/24 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01F1/0306 ,  H01F27/24 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/645 ,  H01L24/31 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/41173 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/84424 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102 ,  H05K1/0209 ,  H05K1/165 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K2201/1003 ,  H05K2201/10166 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.