公开(公告)号：US09570377B2

公开(公告)日：2017-02-14

申请号：US14677649

申请日：2015-04-02

申请人： Jeonggi Jin ,  Byung Lyul Park ,  Jisoon Park ,  Sukchul Bang ,  Deokyoung Jung

发明人： Jeonggi Jin ,  Byung Lyul Park ,  Jisoon Park ,  Sukchul Bang ,  Deokyoung Jung

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate including an integrated circuit formed therein, an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit, an intermetal dielectric layer having at least one metal line that is provided on the interlayer dielectric layer and is electrically connected to integrated circuit, and a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate. The through electrode includes a top portion that is capped with a first protection layer capable of preventing a constituent of the through electrode from being diffused away from the through electrode.

摘要翻译： 具有通过电极覆盖有自对准保护层的半导体器件。 半导体器件包括：半导体衬底，其包括形成在其中的集成电路;半导体衬底上的覆盖集成电路的层间介质层;具有至少一个金属线的金属间电介质层，该金属线设置在层间电介质层上并电连接 到集成电路，以及垂直穿透层间电介质层和半导体衬底的贯通电极。 贯通电极包括顶部，该顶部被第一保护层盖住，该第一保护层能够防止通孔的构成物从通孔扩散。

公开(公告)号：US20120139097A1

公开(公告)日：2012-06-07

申请号：US13243806

申请日：2011-09-23

申请人： JEONGGI JIN ,  Yunhyeok Im ,  Chungsun Lee ,  Jung-Hwan Kim ,  Tae-Hong Min

发明人： JEONGGI JIN ,  Yunhyeok Im ,  Chungsun Lee ,  Jung-Hwan Kim ,  Tae-Hong Min

IPC分类号： H01L23/42 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

摘要： Provided are a semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package may include a circuit substrate, a semiconductor chip mounted on the circuit substrate, a chip package interaction disposed between the circuit substrate and the semiconductor chip, a first molding portion covering part of the semiconductor chip and part of the chip package interaction, a second molding portion formed on the first molding portion, and an adhesion portion adhering the first and second molding portions to each other, the adhesion portion being disposed between the first and second molding portions.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括电路基板，安装在电路基板上的半导体芯片，设置在电路基板和半导体芯片之间的芯片封装相互作用，覆盖半导体芯片的一部分的第一模制部分和芯片封装相互作用的一部分， 形成在第一模制部分上的第二模制部分和将第一模制部分和第二模制部分彼此粘合的粘合部分，粘合部分设置在第一和第二模制部分之间。

公开(公告)号：US20150287680A1

公开(公告)日：2015-10-08

申请号：US14677649

申请日：2015-04-02

申请人： Jeonggi Jin ,  Byung Lyul Park ,  Jisoon Park ,  Sukchul Bang ,  Deokyoung Jung

发明人： Jeonggi Jin ,  Byung Lyul Park ,  Jisoon Park ,  Sukchul Bang ,  Deokyoung Jung

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate including an integrated circuit formed therein, an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit, an intermetal dielectric layer having at least one metal line that is provided on the interlayer dielectric layer and is electrically connected to integrated circuit, and a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate. The through electrode includes a top portion that is capped with a first protection layer capable of preventing a constituent of the through electrode from being diffused away from the through electrode.

摘要翻译： 具有通过电极覆盖有自对准保护层的半导体器件。 半导体器件包括：半导体衬底，其包括形成在其中的集成电路;半导体衬底上的覆盖集成电路的层间介质层;具有至少一个金属线的金属间介电层，该金属线设置在层间电介质层上并电连接 到集成电路，以及垂直穿透层间电介质层和半导体衬底的贯通电极。 贯通电极包括顶部，该顶部被第一保护层盖住，该第一保护层能够防止通孔的构成物从通孔扩散。

公开(公告)号：US20150137326A1

公开(公告)日：2015-05-21

申请号：US14463645

申请日：2014-08-19

申请人： Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

发明人： Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

IPC分类号： H01L23/48 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

摘要翻译： 半导体器件包括具有彼此相对的顶表面和底表面的半导体衬底，设置在半导体衬底的顶表面上并且包括集成电路的层间介质层，设置在层间介电层上的金属间介电层 并且包括电连接到集成电路的至少一个金属互连，设置在金属间电介质层上的上部电介质层，贯穿金属间介电层的贯通电极，层间绝缘层和半导体基板， 所述通孔电介质层包围所述贯通电极，并且使所述通孔与所述半导体基板电绝缘。 通孔电介质层包括上电介质层和层间电介质层之间的一个或多个气隙。

公开(公告)号：US09847276B2

公开(公告)日：2017-12-19

申请号：US14463645

申请日：2014-08-19

申请人： Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

发明人： Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

公开(公告)号：US20130075905A1

公开(公告)日：2013-03-28

申请号：US13602581

申请日：2012-09-04

申请人： Ju-il Choi ,  Jeong-Woo Park ,  Jeonggi Jin ,  Hyungseok Kim

发明人： Ju-il Choi ,  Jeong-Woo Park ,  Jeonggi Jin ,  Hyungseok Kim

IPC分类号： H01L23/48 ,  H01L23/532

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A semiconductor device includes a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer.

摘要翻译： 半导体器件包括基板和穿透基板的贯通孔。 通孔在其第一端处具有从基板的第一表面延伸出的突出部分，并且通孔的第二端接近靠近基板的第二相对端的互连线。 润湿层位于通孔和基底之间并且在通孔的突出部分上延伸。 润湿层包括选择的材料，以便当焊球与润湿层耦合时，改善润湿层与接触润湿层的焊球之间的粘合强度，该润湿层在通孔的突出部分上延伸。