公开(公告)号：US20150137326A1

公开(公告)日：2015-05-21

申请号：US14463645

申请日：2014-08-19

申请人： Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

发明人： Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

IPC分类号： H01L23/48 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

摘要翻译： 半导体器件包括具有彼此相对的顶表面和底表面的半导体衬底，设置在半导体衬底的顶表面上并且包括集成电路的层间介质层，设置在层间介电层上的金属间介电层 并且包括电连接到集成电路的至少一个金属互连，设置在金属间电介质层上的上部电介质层，贯穿金属间介电层的贯通电极，层间绝缘层和半导体基板， 所述通孔电介质层包围所述贯通电极，并且使所述通孔与所述半导体基板电绝缘。 通孔电介质层包括上电介质层和层间电介质层之间的一个或多个气隙。

公开(公告)号：US20150279825A1

公开(公告)日：2015-10-01

申请号：US14669291

申请日：2015-03-26

申请人： Pil-Kyu KANG ,  Byung Lyul PARK ,  Taeyeong KIM ,  Yeun-Sang PARK ,  Dosun LEE ,  Ho-Jin LEE ,  Jinho CHUN ,  Ju-il CHOI ,  Yi Koan HONG

发明人： Pil-Kyu KANG ,  Byung Lyul PARK ,  Taeyeong KIM ,  Yeun-Sang PARK ,  Dosun LEE ,  Ho-Jin LEE ,  Jinho CHUN ,  Ju-il CHOI ,  Yi Koan HONG

IPC分类号： H01L25/16 ,  H01L23/538 ,  H01L23/495 ,  H01L21/48 ,  H01L21/768 ,  H01L21/66 ,  H01L25/00 ,  H01L21/304

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

摘要翻译： 提供具有芯片堆叠和互连端子的半导体器件。 芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。 互连端子电耦合到芯片堆叠。 第一半导体芯片包括第一正面和第一背面。 第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。 第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。 第一前表面和第二前表面彼此面对。 第三前表面和第二后侧表面彼此面对。

公开(公告)号：US20130210222A1

公开(公告)日：2013-08-15

申请号：US13758239

申请日：2013-02-04

申请人： Ho-Jin LEE ,  Kyu-ha LEE ,  Gilheyun CHOI ,  YongSoon CHOI ,  Pil-Kyu KANG ,  Byung-Lyul PARK ,  Hyunsoo CHUNG

发明人： Ho-Jin LEE ,  Kyu-ha LEE ,  Gilheyun CHOI ,  YongSoon CHOI ,  Pil-Kyu KANG ,  Byung-Lyul PARK ,  Hyunsoo CHUNG

IPC分类号： H01L21/768 ,  H01L23/00

CPC分类号： H01L21/768 ,  H01L21/02271 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.

摘要翻译： 在一个实施例中，该方法包括在基层中形成导电通孔结构。 基层具有第一表面和第二表面，并且第二表面与第一表面相对。 该方法还包括去除基底层的第二表面以暴露导电通路结构，使得导电通孔结构从第二表面突出，并且在第二表面上形成第一下绝缘层，使得导电通孔的端表面 结构保持由第一下绝缘层暴露。

公开(公告)号：US20130200525A1

公开(公告)日：2013-08-08

申请号：US13718580

申请日：2012-12-18

申请人： Ho-Jin LEE ,  Pil-Kyu KANG ,  Kyu-Ha LEE ,  Byung-Lyul PARK ,  Hyun-Soo CHUNG ,  Gil-Heyun CHOI

发明人： Ho-Jin LEE ,  Pil-Kyu KANG ,  Kyu-Ha LEE ,  Byung-Lyul PARK ,  Hyun-Soo CHUNG ,  Gil-Heyun CHOI

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.

摘要翻译： 一种半导体器件，包括下层，在下层的第一侧上的绝缘层，绝缘层中的互连结构，下层中的通孔结构。 通孔结构突出到绝缘层和互连结构中。

公开(公告)号：US20130062719A1

公开(公告)日：2013-03-14

申请号：US13614730

申请日：2012-09-13

申请人： Pil-Kyu KANG ,  Joong-Han SHIN ,  Byung-Lyul PARK ,  Gil-Heyun CHOI

发明人： Pil-Kyu KANG ,  Joong-Han SHIN ,  Byung-Lyul PARK ,  Gil-Heyun CHOI

IPC分类号： H01L31/0232

CPC分类号： G02B6/4206 ,  G02B6/12004 ,  G02B6/42 ,  G02B6/4201 ,  G02B6/4204 ,  H01L31/0232

摘要： An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.

摘要翻译： 提供光输入/输出（I / O）设备。 该装置包括：包括上沟槽的衬底; 布置在所述衬底的上沟槽内的波导; 光电检测器，设置在所述衬底的上沟槽内，并且包括光学连接到所述波导的端面的第一端面; 以及插入在波导的端面与光检测器的第一端面之间的透光绝缘层。

公开(公告)号：US20110188828A1

公开(公告)日：2011-08-04

申请号：US12968488

申请日：2010-12-15

申请人： Pil-Kyu KANG ,  Dae Lok BAE ,  Gil Heyun CHOI ,  Jong Myeong LEE

发明人： Pil-Kyu KANG ,  Dae Lok BAE ,  Gil Heyun CHOI ,  Jong Myeong LEE

IPC分类号： G02B6/02

CPC分类号： H01L21/7624 ,  G02B6/02

摘要： A photo-electric integrated circuit device comprises an on-die optical input/output device. The on-die optical input/output device comprises a substrate having a trench, a lower cladding layer disposed in the trench and having an upper surface lower than an upper surface of the substrate, and a core disposed on the lower cladding layer at a distance from sidewalls of the trench and having an upper surface at substantially the same level as the upper surface of the substrate.

摘要翻译： 光电集成电路器件包括一个片上光输入/输出器件。 片上光输入/输出装置包括具有沟槽的衬底，设置在沟槽中的下包层，并且具有比衬底的上表面低的上表面，以及一距离设置在下包层上的芯 从沟槽的侧壁开始并且具有与衬底的上表面基本相同的高度的上表面。

公开(公告)号：US20120025265A1

公开(公告)日：2012-02-02

申请号：US13191902

申请日：2011-07-27

申请人： Ho-Chul JI ,  Kyoung Won NA ,  Kyoung Ho HA ,  Pil-Kyu KANG

发明人： Ho-Chul JI ,  Kyoung Won NA ,  Kyoung Ho HA ,  Pil-Kyu KANG

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： G02B6/12004 ,  G02B6/132 ,  G02B6/136 ,  H01L31/02327 ,  H01L31/103 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of manufacturing a photodetector structure is provided. The method includes forming a structural layer by making a trench in a bulk silicon substrate and filling the trench with a cladding material, forming a single-crystallized silicon layer on the structural layer, and forming a germanium layer on the single-crystallized silicon layer.

摘要翻译： 提供了一种制造光电检测器结构的方法。 该方法包括通过在体硅衬底中形成沟槽并用包覆材料填充沟槽来形成结构层，在结构层上形成单结晶硅层，并在单结晶硅层上形成锗层。

公开(公告)号：US20110223725A1

公开(公告)日：2011-09-15

申请号：US13044703

申请日：2011-03-10

申请人： Pil-Kyu KANG ,  Dae-Lok BAE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE

发明人： Pil-Kyu KANG ,  Dae-Lok BAE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/1203

摘要： A method of manufacturing a buried wiring type substrate comprises implanting hydrogen ions into a single crystalline substrate through a first surface thereof to form an ion implantation region, forming a conductive layer comprising a metal on the first surface of the single crystalline substrate, forming an insulation layer comprising silicon oxide on the conductive layer, bonding the insulation layer to a support substrate to form a preliminary buried wiring type substrate, and separating the single crystalline substrate at the ion implantation region to form a single crystalline semiconductor layer on the conductive layer.

摘要翻译： 一种掩埋布线型衬底的制造方法，包括通过其第一表面将氢离子注入单晶衬底以形成离子注入区，在单晶衬底的第一表面上形成包含金属的导电层，形成绝缘层 在导电层上包含氧化硅的层，将绝缘层粘合到支撑衬底上以形成预埋掩埋布线型衬底，并且在离子注入区域处分离单晶衬底，以在导电层上形成单晶半导体层。