公开(公告)号：US20160155724A1

公开(公告)日：2016-06-02

申请号：US14955124

申请日：2015-12-01

Applicant: Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

Inventor： Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/03616 ,  H01L2224/0392 ,  H01L2224/04 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14515 ,  H01L2224/16146 ,  H01L2224/73251 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/00012 ,  H01L22/00 ,  H01L21/304 ,  H01L2221/68304 ,  H01L2221/68381 ,  H01L21/78

Abstract: Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

Abstract translation: 提供具有堆叠结构的半导体器件及其制造方法。 半导体器件包括至少一个单块，其包括堆叠在其上的第一半导体芯片和第二半导体芯片。 第一和第二半导体芯片中的每一个包括半导体衬底，该半导体衬底包括通孔，半导体衬底的前表面上的电路层和设置在电路层中并且与通孔电连接的前衬垫 。 半导体基板的表面彼此面对。 电路层彼此直接接触，使得半导体芯片彼此结合。

公开(公告)号：US09847276B2

公开(公告)日：2017-12-19

申请号：US14463645

申请日：2014-08-19

Applicant: Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

Inventor： Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

IPC: H01L29/40 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

公开(公告)号：US20140179103A1

公开(公告)日：2014-06-26

申请号：US14108771

申请日：2013-12-17

Applicant: Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

Inventor： Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L21/768

CPC classification number: H01L25/0657 ,  G11C8/00 ,  G11C16/08 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13169 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.

Abstract translation: 提供半导体器件的导电通孔，其沿垂直方向穿过衬底延伸，导电通孔的第一端延伸穿过衬底的第一表面，使得第一端相对于衬底的第一表面在垂直方向上突出 底物。 绝缘层设置在导电通孔的第一端和基板的第一表面上。 除去掩模层图案的上部，使得在导电通孔的第一端上的绝缘层的封盖部分露出。 去除绝缘层的与导电通孔相隔一定距离的一部分，以在绝缘层中形成凹陷。 同时去除导电通孔第一端上的绝缘层的封盖部分。

公开(公告)号：US20170110445A1

公开(公告)日：2017-04-20

申请号：US15391424

申请日：2016-12-27

Applicant: PIL-KYU KANG ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  JU-IL CHOI ,  Yi Koan Hong

Inventor： PIL-KYU KANG ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  JU-IL CHOI ,  Yi Koan Hong

IPC: H01L25/00 ,  H01L21/304 ,  H01L23/48 ,  H01L25/065 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

公开(公告)号：US20150137326A1

公开(公告)日：2015-05-21

申请号：US14463645

申请日：2014-08-19

Applicant: Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

Inventor： Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

Abstract translation: 半导体器件包括具有彼此相对的顶表面和底表面的半导体衬底，设置在半导体衬底的顶表面上并且包括集成电路的层间介质层，设置在层间介电层上的金属间介电层 并且包括电连接到集成电路的至少一个金属互连，设置在金属间电介质层上的上部电介质层，贯穿金属间介电层的贯通电极，层间绝缘层和半导体基板， 所述通孔电介质层包围所述贯通电极，并且使所述通孔与所述半导体基板电绝缘。 通孔电介质层包括上电介质层和层间电介质层之间的一个或多个气隙。

公开(公告)号：US09653430B2

公开(公告)日：2017-05-16

申请号：US14955124

申请日：2015-12-01

Applicant: Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

Inventor： Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/03616 ,  H01L2224/0392 ,  H01L2224/04 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14515 ,  H01L2224/16146 ,  H01L2224/73251 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/00012 ,  H01L22/00 ,  H01L21/304 ,  H01L2221/68304 ,  H01L2221/68381 ,  H01L21/78

Abstract: Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

公开(公告)号：US20150279825A1

公开(公告)日：2015-10-01

申请号：US14669291

申请日：2015-03-26

Applicant: Pil-Kyu KANG ,  Byung Lyul PARK ,  Taeyeong KIM ,  Yeun-Sang PARK ,  Dosun LEE ,  Ho-Jin LEE ,  Jinho CHUN ,  Ju-il CHOI ,  Yi Koan HONG

Inventor： Pil-Kyu KANG ,  Byung Lyul PARK ,  Taeyeong KIM ,  Yeun-Sang PARK ,  Dosun LEE ,  Ho-Jin LEE ,  Jinho CHUN ,  Ju-il CHOI ,  Yi Koan HONG

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/495 ,  H01L21/48 ,  H01L21/768 ,  H01L21/66 ,  H01L25/00 ,  H01L21/304

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract translation: 提供具有芯片堆叠和互连端子的半导体器件。 芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。 互连端子电耦合到芯片堆叠。 第一半导体芯片包括第一正面和第一背面。 第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。 第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。 第一前表面和第二前表面彼此面对。 第三前表面和第二后侧表面彼此面对。

公开(公告)号：US20150243637A1

公开(公告)日：2015-08-27

申请号：US14709840

申请日：2015-05-12

Applicant: Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

Inventor： Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L25/065 ,  G11C8/00 ,  G11C16/08 ,  H01L23/544

Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.

Abstract translation: 提供半导体器件的导电通孔，其沿垂直方向穿过衬底延伸，导电通孔的第一端延伸穿过衬底的第一表面，使得第一端相对于衬底的第一表面在垂直方向上突出 底物。 绝缘层设置在导电通孔的第一端和基板的第一表面上。 除去掩模层图案的上部，使得在导电通孔的第一端上的绝缘层的封盖部分露出。 去除绝缘层的与导电通孔相隔一定距离的一部分，以在绝缘层中形成凹陷。 同时去除导电通孔第一端上的绝缘层的封盖部分。