公开(公告)号：US09530726B2

公开(公告)日：2016-12-27

申请号：US14052691

申请日：2013-10-11

Applicant: Kwang-jin Moon ,  Byung-Iyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

Inventor： Kwang-jin Moon ,  Byung-Iyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.

Abstract translation: 半导体器件包括具有平面部分的顶表面和由平面部分包围的突出部分的通孔结构，并且包括导电结构，该导电结构包括与通孔的顶表面的至少一部分接触的多条导线 结构体。

公开(公告)号：US08952543B2

公开(公告)日：2015-02-10

申请号：US13718580

申请日：2012-12-18

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Byung-Lyul Park ,  Hyun-Soo Chung ,  Gil-Heyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Byung-Lyul Park ,  Hyun-Soo Chung ,  Gil-Heyun Choi

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.

Abstract translation: 一种半导体器件，包括下层，在下层的第一侧上的绝缘层，绝缘层中的互连结构，下层中的通孔结构。 通孔结构突出到绝缘层和互连结构中。

公开(公告)号：US08728850B2

公开(公告)日：2014-05-20

申请号：US13191902

申请日：2011-07-27

Applicant: Ho-Chul Ji ,  Kyoung Won Na ,  Kyoung Ho Ha ,  Pil-Kyu Kang

Inventor： Ho-Chul Ji ,  Kyoung Won Na ,  Kyoung Ho Ha ,  Pil-Kyu Kang

IPC: H01L31/0232 ,  H01L31/028 ,  H01L31/18

CPC classification number: G02B6/12004 ,  G02B6/132 ,  G02B6/136 ,  H01L31/02327 ,  H01L31/103 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a photodetector structure is provided. The method includes forming a structural layer by making a trench in a bulk silicon substrate and filling the trench with a cladding material, forming a single-crystallized silicon layer on the structural layer, and forming a germanium layer on the single-crystallized silicon layer.

Abstract translation: 提供了一种制造光电检测器结构的方法。 该方法包括通过在体硅衬底中形成沟槽并用包覆材料填充沟槽来形成结构层，在结构层上形成单结晶硅层，并在单结晶硅层上形成锗层。

公开(公告)号：US08564139B2

公开(公告)日：2013-10-22

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US20130134603A1

公开(公告)日：2013-05-30

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US08293613B2

公开(公告)日：2012-10-23

申请号：US12926590

申请日：2010-11-29

Applicant: Young-Soo Park ,  Young-Nam Kim ,  Young-Sam Lim ,  Gi-Jung Kim ,  Pil-Kyu Kang

Inventor： Young-Soo Park ,  Young-Nam Kim ,  Young-Sam Lim ,  Gi-Jung Kim ,  Pil-Kyu Kang

IPC: H01L21/331

CPC classification number: H01L21/3221 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.

Abstract translation: 半导体器件的实施例包括半导体衬底，形成在半导体衬底上的第一绝缘层和形成在第一绝缘层上的第一半导体层。 在第一绝缘层和第一半导体层中的至少一个中形成至少一个吸杂区域。 吸气区域包括多个吸气部位，至少一个吸气部位包括沉淀物，分散质，与分散质的界面，堆垛层错和位错中的一个。

公开(公告)号：US20120132986A1

公开(公告)日：2012-05-31

申请号：US13251676

申请日：2011-10-03

Applicant: Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/823487 ,  H01L27/1207

Abstract: A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure.

Abstract translation: 半导体器件包括其上形成有多个水平沟道晶体管的衬底，在衬底上的绝缘层结构并覆盖水平晶体管，以及在绝缘层结构上的多个垂直沟道晶体管。

公开(公告)号：US20120108034A1

公开(公告)日：2012-05-03

申请号：US13239992

申请日：2011-09-22

Applicant: Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Pil-Kyu Kang

Inventor： Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Pil-Kyu Kang

IPC: H01L21/82

CPC classification number: H01L27/10876 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10885 ,  H01L27/1203 ,  H01L2924/00013 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: Provided are a substrate structure which may solve problems generated in a manufacturing process while having a relatively low resistance buried wiring, a method for manufacturing the substrate structure, and a semiconductor device and a method for manufacturing the same using the substrate structure. The substrate structure may include a supporting substrate, an insulating layer disposed on the supporting substrate, a line-shaped conductive layer pattern disposed in the insulating layer to extend in a first direction, and a line-shaped semiconductor pattern disposed in the insulating layer and on the conductive layer pattern to extend in the first direction and having a top surface exposed to the outside of the insulating layer.

Abstract translation: 提供了可以解决制造工艺中产生的问题的基板结构，同时具有相对低的电阻埋地布线，制造基板结构的方法和半导体器件及其使用该基板结构的方法。 衬底结构可以包括支撑衬底，设置在支撑衬底上的绝缘层，设置在绝缘层中以沿第一方向延伸的线状导电层图案和布置在绝缘层中的线状半导体图案，以及 在导电层图案上沿着第一方向延伸并且具有暴露于绝缘层外侧的顶表面。

公开(公告)号：US20120052635A1

公开(公告)日：2012-03-01

申请号：US13221158

申请日：2011-08-30

Applicant: Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-Iyul Park ,  Dong-kak Lee

Inventor： Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-Iyul Park ,  Dong-kak Lee

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/1203

Abstract: A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.

Abstract translation: 公开了一种导电层掩埋型衬底。 基板包括结合到支撑基板的硅氧化层，形成在硅氧化层上的粘合促进层，并且改善硅氧化层和导电层之间的粘附性，其中导电层形成在粘附促进层上 并且包括金属层和形成在导电层上的单晶半导体层。

公开(公告)号：US20110188828A1

公开(公告)日：2011-08-04

申请号：US12968488

申请日：2010-12-15

Applicant: Pil-Kyu KANG ,  Dae Lok BAE ,  Gil Heyun CHOI ,  Jong Myeong LEE

Inventor： Pil-Kyu KANG ,  Dae Lok BAE ,  Gil Heyun CHOI ,  Jong Myeong LEE

IPC: G02B6/02

CPC classification number: H01L21/7624 ,  G02B6/02

Abstract: A photo-electric integrated circuit device comprises an on-die optical input/output device. The on-die optical input/output device comprises a substrate having a trench, a lower cladding layer disposed in the trench and having an upper surface lower than an upper surface of the substrate, and a core disposed on the lower cladding layer at a distance from sidewalls of the trench and having an upper surface at substantially the same level as the upper surface of the substrate.

Abstract translation: 光电集成电路器件包括一个片上光输入/输出器件。 片上光输入/输出装置包括具有沟槽的衬底，设置在沟槽中的下包层，并且具有比衬底的上表面低的上表面，以及一距离设置在下包层上的芯 从沟槽的侧壁开始并且具有与衬底的上表面基本相同的高度的上表面。