公开(公告)号：US20170129972A1

公开(公告)日：2017-05-11

申请号：US15345910

申请日：2016-11-08

申请人： Jeong-Ju PARK ,  Seung-Chul KWON ,  Eun-Sung KIM ,  Kyeong-Mi LEE ,  Shi-Yong YI ,  Tsuyosh KUROSAWA ,  Katsumi OHMORI ,  Tasuku MATSUMIYA

发明人： Jeong-Ju PARK ,  Seung-Chul KWON ,  Eun-Sung KIM ,  Kyeong-Mi LEE ,  Shi-Yong YI ,  Tsuyosh KUROSAWA ,  Katsumi OHMORI ,  Tasuku MATSUMIYA

IPC分类号： C08F12/08 ,  H01L27/108 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  C08F299/04 ,  C08F20/28

CPC分类号： G03F7/165 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00 ,  C08F20/28 ,  C08L53/00 ,  G03F7/0002 ,  G03F7/0035 ,  G03F7/2022 ,  G03F7/2059 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L28/00

摘要： In a method of forming patterns, an object layer is formed on a substrate. Guide patterns are formed on the object layer. A brush layer is formed using a brush polymer on surfaces of the guide patterns. The brush polymer includes at least one of a first brush polymer and a second brush polymer. The first brush polymer includes a hydrophobic repeating unit and a hydrophilic terminal group having at least two hydroxyl groups. The second brush polymer includes a hydrophobic repeating unit and a hydrophilic random repeating unit having a hydroxyl group. A self-aligned layer is formed using a block copolymer on the brush layer to form blocks aligned around the guide patterns. At least a portion of the blocks is transferred to the object layer.

公开(公告)号：US20130089986A1

公开(公告)日：2013-04-11

申请号：US13608403

申请日：2012-09-10

申请人： Jeong-ju PARK ,  Kyoung-mi KIM ,  Min-jung KIM ,  Dong-jun LEE ,  Boo-deuk KIM

发明人： Jeong-ju PARK ,  Kyoung-mi KIM ,  Min-jung KIM ,  Dong-jun LEE ,  Boo-deuk KIM

IPC分类号： G03F7/20 ,  H01L21/32

CPC分类号： H01L21/32139 ,  G03F7/0392 ,  G03F7/095 ,  G03F7/2022 ,  G03F7/203 ,  H01L21/0274

摘要： A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.

摘要翻译： 形成半导体器件的图案的方法可以包括形成光致抗蚀剂层，该光致抗蚀剂层包括光酸产生剂（PAG）和光产生剂（PBG），首先在光致抗蚀剂层的第一暴露部分中从PAG产生酸 并且在所述光致抗蚀剂层的第二暴露部分中通过将所述第一暴露部分的一部分暴露并中和所述酸而从所述PBG生成碱。 该方法还可以包括在第一和第二次曝光和去除其中产生酸的第一暴露部分的光致抗蚀剂层以形成解封的光致抗蚀剂层之后烘烤光致抗蚀剂层，以及通过去除去封闭的光刻胶层形成光致抗蚀剂图案 通过使用开发人员。

公开(公告)号：US20120064724A1

公开(公告)日：2012-03-15

申请号：US13222447

申请日：2011-08-31

申请人： Bo-hee Lee ,  Kyoung-mi Kim ,  Jeong-ju Park ,  Mi-ra Park ,  Jae-ho Kim ,  Young-ho Kim

发明人： Bo-hee Lee ,  Kyoung-mi Kim ,  Jeong-ju Park ,  Mi-ra Park ,  Jae-ho Kim ,  Young-ho Kim

IPC分类号： H01L21/308

CPC分类号： H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： Methods of forming a pattern of a semiconductor device including performing a double patterning process without using an atomic layer deposition (ALD) oxide film are provided. The methods may include forming a mask pattern on a substrate; forming a chemical attach process (CAP) material layer covering at least a portion of the mask pattern; forming a CAP adhesive layer by adhering at least a portion of the CAP material layer to the mask pattern by using a first baking process and a first development process; forming an interlayer covering at least a portion of the mask pattern and the CAP adhesive layer; and removing the mask pattern and the interlayer while allowing the CAP adhesive layer to remain by using a second baking process and a second development process.

摘要翻译： 提供了形成半导体器件的图案的方法，包括不使用原子层沉积（ALD）氧化物膜来执行双重图案化工艺。 所述方法可以包括在衬底上形成掩模图案; 形成覆盖所述掩模图案的至少一部分的化学附着工艺（CAP）材料层; 通过使用第一烘烤处理和第一显影处理将CAP材料层的至少一部分粘附到掩模图案上形成CAP粘合剂层; 形成覆盖所述掩模图案和所述CAP粘合剂层的至少一部分的中间层; 以及通过使用第二烘烤处理和第二显影处理使CAP粘合剂层保持不动，从而去除掩模图案和中间层。

公开(公告)号：US20110300712A1

公开(公告)日：2011-12-08

申请号：US13103375

申请日：2011-05-09

申请人： Kyoung-Mi Kim ,  Jeong-Ju Park ,  Mi-Ra Park ,  Bo-Hee Lee ,  Jae-Ho Kim ,  Young-Ho Kim

发明人： Kyoung-Mi Kim ,  Jeong-Ju Park ,  Mi-Ra Park ,  Bo-Hee Lee ,  Jae-Ho Kim ,  Young-Ho Kim

IPC分类号： H01L21/308 ,  H01L21/312

CPC分类号： H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11521

摘要： Methods of forming a photoresist pattern include forming a first photoresist pattern on a substrate and treating the first photoresist pattern with plasma that modifies etching characteristics of the first photoresist pattern. This modification may include making the first photoresist pattern more susceptible to removal during subsequent processing. The plasma-treated first photoresist pattern is covered with a second photoresist layer, which is patterned into a second photoresist pattern that contacts sidewalls of the plasma-treated first photoresist pattern. The plasma-treated first photoresist pattern is selectively removed from the substrate to reveal the remaining second photoresist pattern. The second photoresist pattern is used as an etching mask during the selective etching of a portion of the substrate (e.g., target layer). The use of the second photoresist pattern as an etching mask may yield narrower linewidths in the etched portion of the substrate than are achievable using the first photoresist pattern alone.

摘要翻译： 形成光致抗蚀剂图案的方法包括在基板上形成第一光致抗蚀剂图案，并用等离子体处理第一光致抗蚀剂图案，其改变第一光致抗蚀剂图案的蚀刻特性。 该修改可以包括使第一光致抗蚀剂图案在随后的处理期间更易于去除。 等离子体处理的第一光致抗蚀剂图案被第二光致抗蚀剂层覆盖，第二光致抗蚀剂层被图案化成与等离子体处理的第一光致抗蚀剂图案的侧壁接触的第二光致抗蚀剂 从衬底选择性地去除等离子体处理的第一光致抗蚀剂图案以显示剩余的第二光致抗蚀剂图案。 在选择性蚀刻基板（例如，目标层）的一部分期间，将第二光致抗蚀剂图案用作蚀刻掩模。 使用第二光致抗蚀剂图案作为蚀刻掩模可以在衬底的蚀刻部分中产生比仅使用第一光致抗蚀剂图案可实现的更窄的线宽。

公开(公告)号：US20050095782A1

公开(公告)日：2005-05-05

申请号：US11000943

申请日：2004-12-02

申请人： Jeong-Ju Park

发明人： Jeong-Ju Park

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： Lower electrode contact structures and methods of forming the same provide an interface having a large surface area between a lower electrode and the underlying layers. The lower electrode is in contact with a contact plug and an insulation layer in which the contact plug is buried. At least one supporting layer protrudes upright along the outer peripheral edge of the top surface of the contact plug. The interface between the lower electrode and the underlying layers is thus increased by the supporting layer(s) so that the lower electrode and the underlying layers will solidly adhere to each other.

摘要翻译： 下电极接触结构及其形成方法提供了在下电极和下层之间具有大表面积的界面。 下电极与接触插塞和绝缘层接触，其中接触插头被埋入其中。 至少一个支撑层沿着接触插塞的上表面的外周缘直立突出。 因此，下电极和下层之间的界面由支撑层增加，使得下电极和下层将彼此牢固地粘附。

公开(公告)号：US08685865B2

公开(公告)日：2014-04-01

申请号：US13608403

申请日：2012-09-10

申请人： Jeong-ju Park ,  Kyoung-mi Kim ,  Min-jung Kim ,  Dong-jun Lee ,  Boo-deuk Kim

发明人： Jeong-ju Park ,  Kyoung-mi Kim ,  Min-jung Kim ,  Dong-jun Lee ,  Boo-deuk Kim

IPC分类号： H01L21/32 ,  G03F7/20

CPC分类号： H01L21/32139 ,  G03F7/0392 ,  G03F7/095 ,  G03F7/2022 ,  G03F7/203 ,  H01L21/0274

摘要： A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.

摘要翻译： 形成半导体器件的图案的方法可以包括形成光致抗蚀剂层，该光致抗蚀剂层包括光酸产生剂（PAG）和光产生剂（PBG），首先在光致抗蚀剂层的第一暴露部分中从PAG产生酸 并且在所述光致抗蚀剂层的第二暴露部分中通过将所述第一暴露部分的一部分暴露并中和所述酸而从所述PBG生成碱。 该方法还可以包括在第一和第二次曝光和去除其中产生酸的第一暴露部分的光致抗蚀剂层以形成解封的光致抗蚀剂层之后烘烤光致抗蚀剂层，以及通过去除去封闭的光刻胶层形成光致抗蚀剂图案 通过使用开发人员。

公开(公告)号：US20070224758A1

公开(公告)日：2007-09-27

申请号：US11516750

申请日：2006-09-07

申请人： Jeong-Ju Park

发明人： Jeong-Ju Park

IPC分类号： H01L21/8242

CPC分类号： H01L27/10885 ,  H01L21/76831 ,  H01L21/76834 ,  H01L27/10855

摘要： Embodiments of the invention provide a semiconductor memory device and a method for fabricating the semiconductor memory device. The semiconductor memory device comprises a source region and a drain region disposed in a semiconductor substrate; a buried contact disposed on and electrically connected to the source region of the transistor; and a direct contact disposed on and electrically connected to the drain region of the transistor, wherein an upper surface of the direct contact is disposed at a different height than an upper surface of the buried contact. The semiconductor memory device further comprises a bit line disposed on and electrically connected to the direct contact and thereby electrically connected to the drain region; and a lower electrode of a capacitor disposed on and electrically connected to the buried contact and thereby electrically connected to the source region.

摘要翻译： 本发明的实施例提供半导体存储器件和制造半导体存储器件的方法。 半导体存储器件包括设置在半导体衬底中的源极区域和漏极区域; 设置在晶体管的源极区域上并与之电连接的埋入触点; 以及设置在晶体管的漏极区域并电连接到晶体管的漏极区域的直接接触，其中直接接触件的上表面设置在与埋入接触件的上表面不同的高度处。 所述半导体存储器件还包括位线，其布置在所述直接触点上并电连接到所述直接触点，从而电连接到所述漏极区; 以及电容器的下电极，其布置在所述埋入触点上并电连接到所述掩埋触点，从而电连接到所述源极区。

公开(公告)号：US20050273680A1

公开(公告)日：2005-12-08

申请号：US11122059

申请日：2005-05-05

申请人： Jeong-Ju Park

发明人： Jeong-Ju Park

IPC分类号： H01L21/28 ,  G11C29/00 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522

CPC分类号： H01L21/76895 ,  H01L21/76834 ,  H01L23/5226 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a buffer layer pattern and a related method of manufacture are disclosed. The semiconductor device comprises at least two bit line patterns formed on a semiconductor substrate having a buried insulating interlayer. Each bit line pattern is formed of a bit line and a bit line capping layer pattern formed on the bit line. A buffer layer pattern is formed to cover one of the bit line patterns, and bit line spacers are formed on sidewalls of the remaining bit line patterns. A planarized insulating interlayer covers the buffer layer pattern and the bit line spacers. A bit line contact hole passing through the planarized insulating interlayer, the buffer layer pattern, and the bit line capping layer pattern, is formed on the bit line.

摘要翻译： 公开了一种具有缓冲层图案和相关制造方法的半导体器件。 半导体器件包括形成在具有掩埋绝缘中间层的半导体衬底上的至少两个位线图案。 每个位线图案由位线和形成在位线上的位线覆盖层图案形成。 形成缓冲层图形以覆盖位线图案之一，并且位线间隔件形成在剩余位线图案的侧壁上。 平坦化的绝缘夹层覆盖缓冲层图案和位线间隔物。 在位线上形成穿过平坦化绝缘夹层，缓冲层图案和位线封盖层图案的位线接触孔。

公开(公告)号：US06861690B2

公开(公告)日：2005-03-01

申请号：US10634898

申请日：2003-08-06

申请人： Jeong-Ju Park

发明人： Jeong-Ju Park

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L25/208 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/91 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： Lower electrode contact structures and methods of forming the same provide an interface having a large surface area between a lower electrode and the underlying layers. The lower electrode is in contact with a contact plug and an insulation layer in which the contact plug is buried. At least one supporting layer protrudes upright along the outer peripheral edge of the top surface of the contact plug. The interface between the lower electrode and the underlying layers is thus increased by the supporting layer(s) so that the lower electrode and the underlying layers will solidly adhere to each other.

公开(公告)号：US08551689B2

公开(公告)日：2013-10-08

申请号：US13117667

申请日：2011-05-27

申请人： Mi-Ra Park ,  Kyoung-Mi Kim ,  Jeong-Ju Park ,  Bo-Hee Lee ,  Jae-Ho Kim ,  Young-Ho Kim

发明人： Mi-Ra Park ,  Kyoung-Mi Kim ,  Jeong-Ju Park ,  Bo-Hee Lee ,  Jae-Ho Kim ,  Young-Ho Kim

IPC分类号： G03F7/26

CPC分类号： H01L21/0273 ,  G03F7/0035 ,  G03F7/091 ,  G03F7/40

摘要： A method of manufacturing a semiconductor device using a photolithography process may include forming an anti-reflective layer and a first photoresist film on a lower surface. The first photoresist film may be exposed to light and a first photoresist pattern having a first opening may be formed by developing the first photoresist film. A plasma treatment can be performed on the first photoresist pattern and a second photoresist film may be formed on the first photoresist pattern, which may be exposed to light. A second photoresist pattern may be formed to have a second opening by developing the second photoresist film. Here, the second opening may be substantially narrower than the first opening.

摘要翻译： 使用光刻工艺制造半导体器件的方法可以包括在下表面上形成抗反射层和第一光致抗蚀剂膜。 可以将第一光致抗蚀剂膜暴露于光，并且可以通过显影第一光致抗蚀剂膜来形成具有第一开口的第一光致抗蚀剂图案。 可以在第一光致抗蚀剂图案上进行等离子体处理，并且可以在可以暴露于光的第一光致抗蚀剂图案上形成第二光致抗蚀剂膜。 可以通过显影第二光致抗蚀剂膜来形成第二光致抗蚀剂图案以具有第二开口。 这里，第二开口可以比第一开口窄得多。