公开(公告)号：USRE46666E1

公开(公告)日：2018-01-09

申请号：US14215033

申请日：2014-03-16

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/52 ,  H01L23/043 ,  H01L23/31

CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of the board body, and a second power pad, a second ground pad and a second signal pad are disposed on the back surface of the board body. The second power pad, the second ground pad and the second signal pad are electrically connected to the first power pad, the first ground pad and the first signal pad, respectively. An internal terminal interconnection is provided in a bulk region of the board body or on a surface of the board body. The internal terminal interconnection electrically connects the first internal terminal pad to the second internal terminal pad. A semiconductor package employing the package board is also provided.

公开(公告)号：US20140097513A1

公开(公告)日：2014-04-10

申请号：US13963598

申请日：2013-08-09

申请人： Jong-joo Lee

发明人： Jong-joo Lee

IPC分类号： H01L23/538

CPC分类号： H01L23/538 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19105 ,  H01L2924/00

摘要： A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed.

摘要翻译： 封装封装（PoP）型封装包括具有第一无源元件和安装在第一基板上的第一半导体器件的第一半导体封装以及安装在第二基板上的具有第二半导体器件的第二半导体封装。 第一无源元件电连接到第二半导体器件。 还讨论了相关设备。

公开(公告)号：US08643178B2

公开(公告)日：2014-02-04

申请号：US13775580

申请日：2013-02-25

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

摘要翻译： 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

公开(公告)号：US08410611B2

公开(公告)日：2013-04-02

申请号：US13344634

申请日：2012-01-06

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

公开(公告)号：US08319324B2

公开(公告)日：2012-11-27

申请号：US11950990

申请日：2007-12-05

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/36

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L25/18 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311

摘要： Provided are a high I/O semiconductor chip package in which a processor and a memory device are connected to each other via through electrodes and a method of manufacturing the high I/O semiconductor chip package. The high I/O semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, each memory device being arranged in a matrix in chip regions partitioned by a scribe region; a second semiconductor chip stacked on the first semiconductor chip; and a plurality of through electrodes arranged along peripheral portions of the memory devices and connecting the first and second semiconductor chips to the second circuit patterns of the substrate.

摘要翻译： 提供了一种高I / O半导体芯片封装，其中处理器和存储器件通过电极彼此连接，以及制造高I / O半导体芯片封装的方法。 高I ​​/ O半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 第一半导体芯片，包括布置在所述基板上的多个存储器件，每个存储器件以矩阵布置在由划线区域划分的芯片区域中; 堆叠在第一半导体芯片上的第二半导体芯片; 以及沿着存储装置的周边部分布置的多个通孔，并将第一和第二半导体芯片连接到基板的第二电路图案。

公开(公告)号：US20120049352A1

公开(公告)日：2012-03-01

申请号：US13208455

申请日：2011-08-12

申请人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

发明人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

摘要： A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

摘要翻译： 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。

公开(公告)号：US08125068B2

公开(公告)日：2012-02-28

申请号：US12545323

申请日：2009-08-21

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/525 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/06136 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/4824 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/29075 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure.

摘要翻译： 公开了一种半导体芯片，其包括穿过基板的芯片通孔插塞，其半导体叠层，其半导体器件封装以及具有该半导体芯片的电子设备。 所述半导体芯片包括：包括内部半导体电路的基板，形成在所述基板上的导电再分布结构，所述导电再分布结构包括导电再分配互连和通过插头的导电再分布，其中所述再分配经由插头连接到所述内部半导体电路; 形成在所述基板上的导电芯片焊盘，以及被配置为穿透所述基板并电连接到所述再分布结构的导电芯片通孔插头。

公开(公告)号：US08120176B2

公开(公告)日：2012-02-21

申请号：US12722794

申请日：2010-03-12

申请人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

发明人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.

摘要翻译： 在一个实施例中，半导体器件包括半导体衬底和设置在其上的接合焊盘。 半导体器件还包括依次堆叠在半导体衬底上的钝化层，缓冲层和绝缘层。 根据一个方面，在钝化层，缓冲层和绝缘层内限定第一凹槽，以露出焊盘的至少一个区域，并且在绝缘层内限定第二凹槽，以暴露至少一个区域 缓冲层，并且与第一凹部间隔开，使得绝缘层的一部分插入其间。 此外，半导体器件包括设置在第一和第二凹槽内的导电焊料凸块。 导电焊料凸块可以连接到第一凹槽中的焊盘，并且通过延伸到第二凹部中的导电焊料凸块的突起被缓冲层支撑。

公开(公告)号：US20110316159A1

公开(公告)日：2011-12-29

申请号：US13224670

申请日：2011-09-02

申请人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

发明人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US07675181B2

公开(公告)日：2010-03-09

申请号：US11951024

申请日：2007-12-05

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48

CPC分类号： H01L25/18 ,  H01L23/481 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate.

摘要翻译： 提供一种平面多半导体芯片封装，其中处理器和存储器件经由通孔彼此连接，以及制造平面多芯片封装的方法。 平面多晶半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 包括布置在所述基板上的多个存储器件的第一半导体芯片，其中第一存储器件围绕第二存储器件的至少一部分; 堆叠在第一半导体芯片上并对应于第二存储器件的第二半导体芯片; 以及布置在第二存储器件上并将第一和第二半导体芯片连接到基板的第二电路图案的多个贯通电极。