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公开(公告)号：US08039309B2
公开(公告)日：2011-10-18
申请号：US12116459
申请日：2008-05-07
IPC分类号： H01L21/00
CPC分类号： H01L21/561 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/3677 , H01L23/5389 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2221/68377 , H01L2224/04105 , H01L2224/12105 , H01L2224/13099 , H01L2224/16 , H01L2224/32188 , H01L2224/92 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/10329 , H01L2924/10336 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/0401
摘要： A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.
摘要翻译： 使用导电板作为基板的集成电路封装的方法包括通过在导电板的一部分厚度上冲压或选择性地去除导电板的一部分，然后电连接半导体管芯 到导电板上形成的图案。 该方法还包括用密封剂封装至少一部分模具和导电板，并从与图案化侧相对的一侧去除导电板的一部分，以形成基于形成的图案的导电迹线。
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公开(公告)号：US20110250720A1
公开(公告)日：2011-10-13
申请号：US13110144
申请日：2011-05-18
IPC分类号： H01L21/60
CPC分类号： H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05599 , H01L2224/05647 , H01L2224/13009 , H01L2224/13099 , H01L2224/13147 , H01L2224/81136 , H01L2224/812 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.
摘要翻译： 管芯接合系统和方法包括具有前侧，后侧和通过硅通孔的完全填充的上模，从上模的后侧突出的完全填充的硅通孔的一部分。 下模包括前侧，后侧和部分填充的硅通孔，其形成为限定暴露于模具的前侧的通孔开口，部分填充的硅通孔的一部分从背面侧突出 下模。 互连通过硅通孔的上模的突出部分的外表面与下模具中的通孔开口的内表面结合。
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公开(公告)号：US08193093B2
公开(公告)日：2012-06-05
申请号：US13110144
申请日：2011-05-18
CPC分类号： H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05599 , H01L2224/05647 , H01L2224/13009 , H01L2224/13099 , H01L2224/13147 , H01L2224/81136 , H01L2224/812 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.
摘要翻译： 管芯接合系统和方法包括具有前侧，后侧和通过硅通孔的完全填充的上模，从上模的后侧突出的完全填充的硅通孔的一部分。 下模包括前侧，后侧和部分填充的硅通孔，其形成为限定暴露于模具的前侧的通孔开口，部分填充的硅通孔的一部分从背面侧突出 下模。 互连通过硅通孔的上模的突出部分的外表面与下模具中的通孔开口的内表面结合。
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公开(公告)号：US20100320575A9
公开(公告)日：2010-12-23
申请号：US12369441
申请日：2009-02-11
IPC分类号： H01L23/498 , H01L21/50 , H01L21/768
CPC分类号： H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05599 , H01L2224/05647 , H01L2224/13009 , H01L2224/13099 , H01L2224/13147 , H01L2224/81136 , H01L2224/812 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.
摘要翻译： 管芯接合系统和方法包括具有前侧，后侧和通过硅通孔的完全填充的上模，从上模的后侧突出的完全填充的硅通孔的一部分。 下模包括前侧，后侧和部分填充的硅通孔，其形成为限定暴露于模具的前侧的通孔开口，部分填充的硅通孔的一部分从背面侧突出 下模。 互连通过硅通孔的上模的突出部分的外表面与下模具中的通孔开口的内表面结合。
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公开(公告)号：US20100200961A1
公开(公告)日：2010-08-12
申请号：US12369441
申请日：2009-02-11
IPC分类号： H01L23/498 , H01L21/50 , H01L21/768
CPC分类号： H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05599 , H01L2224/05647 , H01L2224/13009 , H01L2224/13099 , H01L2224/13147 , H01L2224/81136 , H01L2224/812 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.
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公开(公告)号：US07635914B2
公开(公告)日：2009-12-22
申请号：US11804237
申请日：2007-05-17
IPC分类号： H01L23/12
CPC分类号： H01L25/105 , H01L23/3121 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2224/85 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).
摘要翻译： 在制造具有封装封装结构的半导体器件（100）的方法和系统中，形成基底层叠衬底（BLS）（110）以包括基部中心部分（112）和周边部分（114） 由屏障元件（120）隔开。 阻挡元件（120）形成围绕基部中心部分（112）的周壁（118）。 在BLS（110）的周边部分（114）上设置框架形顶层叠基板（TLS）（130）。 TLS（130）具有与由周壁（118）围绕的基部中心部分（112）匹配以形成空腔（140）的敞开的顶部中心部分（132）。 每个设置在TLS的顶部接触焊盘（134）和BLS（110）的周边部分（114）的基部接触焊盘（116）之间的多个导电凸块（150）被形成以提供电气和机械耦合 之间。 阻挡元件（120）在空腔（140）和多个导电凸块（150）之间形成密封。
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公开(公告)号：US20080283992A1
公开(公告)日：2008-11-20
申请号：US11804237
申请日：2007-05-17
CPC分类号： H01L25/105 , H01L23/3121 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2224/85 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).
摘要翻译： 在制造具有封装封装结构的半导体器件（100）的方法和系统中，形成基底层叠衬底（BLS）（110）以包括基部中心部分（112）和周边部分（114） 由屏障元件（120）隔开。 阻挡元件（120）形成围绕基部中心部分（112）的周壁（118）。 在BLS（110）的周边部分（114）上设置框架形顶层叠基板（TLS）（130）。 TLS（130）具有与由周壁（118）围绕的基部中心部分（112）匹配以形成空腔（140）的敞开的顶部中心部分（132）。 每个设置在TLS的顶部接触焊盘（134）和BLS（110）的周边部分（114）的基部接触焊盘（116）之间的多个导电凸块（150）被形成以提供电气和机械耦合 之间。 阻挡元件（120）在空腔（140）和多个导电凸块（150）之间形成密封。
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公开(公告)号：US20080280394A1
公开(公告)日：2008-11-13
申请号：US12116459
申请日：2008-05-07
CPC分类号： H01L21/561 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/3677 , H01L23/5389 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2221/68377 , H01L2224/04105 , H01L2224/12105 , H01L2224/13099 , H01L2224/16 , H01L2224/32188 , H01L2224/92 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/10329 , H01L2924/10336 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/0401
摘要： A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.
摘要翻译： 使用导电板作为基板的集成电路封装的方法包括通过在导电板的一部分厚度上冲压或选择性地去除导电板的一部分，然后电连接半导体管芯 到导电板上形成的图案。 该方法还包括用密封剂封装至少一部分模具和导电板，并从与图案化侧相对的一侧去除导电板的一部分，以形成基于形成的图案的导电迹线。
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公开(公告)号：US06888255B2
公开(公告)日：2005-05-03
申请号：US10449212
申请日：2003-05-30
IPC分类号： H01L23/498 , H05K1/11 , H05K3/24 , H05K3/34 , H01L23/48
CPC分类号： H01L23/49811 , H01L2224/16225 , H01L2224/16237 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H05K1/111 , H05K3/243 , H05K3/245 , H05K3/3452 , H05K2201/035 , Y02P70/611 , H01L2924/00 , H01L2224/0401
摘要： In accordance with the present invention, a built-up bump pad structure and method for the same are provided. The bump pad structure includes a substrate, a bump pad disposed upon the substrate, a solder mask disposed upon the substrate defining an opening around the bump pad, and a conductive material deposited upon the bump pad such that the conductive material at least partially fills the opening around the bump pad.
摘要翻译： 根据本发明，提供了一种用于其的积层凸块焊盘结构及其方法。 所述凸块焊盘结构包括衬底，设置在所述衬底上的凸块焊盘，设置在所述衬底上的限定围绕所述凸块焊盘的开口的焊接掩模以及沉积在所述凸块焊盘上的导电材料，使得所述导电材料至少部分地填充 打开碰撞垫周围。
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公开(公告)号：US20110183464A1
公开(公告)日：2011-07-28
申请号：US12694012
申请日：2010-01-26
IPC分类号： H01L21/60
CPC分类号： H01L21/6836 , C09J5/06 , C09J2203/326 , C09J2205/302 , H01L21/561 , H01L21/565 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2221/68381 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/81001 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/83191 , H01L2224/83192 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01043 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19041 , H01L2924/20105 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要： A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.
摘要翻译： 使用贯通基板通孔（TSV）晶片形成堆叠的电子产品的方法包括使用具有第一剥离温度的第一粘合材料将第一载体晶片安装到TSV晶片的顶侧。 TSV晶片从TSV晶片的底侧变薄以形成薄的TSV晶片。 使用第二粘合剂材料将第二载体晶片安装到TSV晶片的底侧，第二粘合材料具有与第一脱粘温度相比更高的第二剥离温度。 将薄化的TSV晶片加热到高于第一脱粘温度的温度，以从稀薄的TSV晶片去除第一载体晶片。 至少一个单片IC芯片被结合到形成在薄化的TSV晶片的顶表面上的TSV模具，以形成堆叠的电子制品。
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