公开(公告)号：US07304249B2

公开(公告)日：2007-12-04

申请号：US10837701

申请日：2004-05-04

申请人： Sung-Gue Lee ,  Yong-Il Kim

发明人： Sung-Gue Lee ,  Yong-Il Kim

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K3/243 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2203/0597 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204

摘要： Bonding pad(s) for a printed circuit board with circuit patterns are provided. The bonding pad(s) include a plurality of copper patterns formed on the PCB and electrically connected to the circuit patterns, a filler filled between the copper patterns such that an upper surface of the copper pattern is exposed, and a plating layer applied at an upper surface of the copper patterns. An interval between wire bonding pad(s) is reduced by preventing a nickel plating layer and a gold plating layer from protruding at a lower portion of a copper pattern when they are formed on the copper patterns.

摘要翻译： 提供了具有电路图案的印刷电路板的接合焊盘。 焊盘包括形成在PCB上并电连接到电路图案的多个铜图案，填充在铜图案之间的填充物，使得铜图案的上表面暴露，并且镀覆层 铜图案的上表面。 通过防止镀镍层和镀金层在铜图案上形成时在铜图案的下部突出，从而降低引线接合焊盘之间的间隔。

公开(公告)号：US06954985B2

公开(公告)日：2005-10-18

申请号：US10043146

申请日：2002-01-14

申请人： Sung Gue Lee ,  Sung Sik Cho ,  Yong Il Kim ,  Yong Soon Jang ,  Ho Sung Choi ,  Sang Jin Kong ,  Young Hwan Kim

发明人： Sung Gue Lee ,  Sung Sik Cho ,  Yong Il Kim ,  Yong Soon Jang ,  Ho Sung Choi ,  Sang Jin Kong ,  Young Hwan Kim

IPC分类号： H05K3/28 ,  H05K3/00 ,  H05K3/12 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

CPC分类号： H05K3/0094 ,  H05K3/1225 ,  H05K3/28 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0278 ,  H05K2203/0557 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49135 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

摘要： A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.

摘要翻译： 用于印刷电路板的孔堵塞方法，根据本发明的孔堵装置及其制造方法，其中用于选择性地暴露印刷电路板的通孔，通孔和表面图案的掩模位于 具有通孔和通孔的电路板电连接板和表面上形成的电路图案和绝缘材料，通过邻接和推动板的表面上的材料而被堵塞在通孔中。 因此，绝缘材料可以没有空隙而平滑地插入，通过将绝缘材料刚好插入电路图案之间的空间中的电路图案的高度来简化处理，因此可以防止电路图案的损坏。

公开(公告)号：US20050098347A1

公开(公告)日：2005-05-12

申请号：US10981778

申请日：2004-11-05

申请人： Jung-Ho Hwang ,  Sung-Gue Lee ,  Sang-Min Lee ,  Joon-Wook Han ,  Tae-Sik Eo ,  Yu-Seock Yang

发明人： Jung-Ho Hwang ,  Sung-Gue Lee ,  Sang-Min Lee ,  Joon-Wook Han ,  Tae-Sik Eo ,  Yu-Seock Yang

IPC分类号： H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K1/00 ,  H05K3/02

CPC分类号： H05K3/4647 ,  H05K3/0097 ,  H05K3/423 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09845 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K2203/1536 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A fabricating method for a multi-layer printed circuit board comprises the steps of: attaching a releasing film at upper and lower surfaces of a center layer and attaching a first metal film to the releasing film, thereby forming a base member; forming a first connection portion on the first metal film by an electroplating process; forming a connection portion that a second connection portion is integrally formed with the first connection portion on the first connection portion; forming a second metal film on the second connection portion so as to be electrically connected to the connection portion; and etching a specific part of the second metal film and thereby forming copper patterns.

摘要翻译： 一种多层印刷电路板的制造方法，包括以下步骤：在中心层的上表面和下表面处附着脱模膜，并将第一金属膜附着到脱模膜，从而形成基材; 通过电镀工艺在第一金属膜上形成第一连接部分; 在所述第一连接部上形成与所述第一连接部一体形成的第二连接部的连接部， 在所述第二连接部分上形成第二金属膜，以便电连接到所述连接部分; 并蚀刻第二金属膜的特定部分，从而形成铜图案。

公开(公告)号：US06803257B2

公开(公告)日：2004-10-12

申请号：US10175912

申请日：2002-06-21

申请人： Sung Gue Lee ,  Yong Il Kim

发明人： Sung Gue Lee ,  Yong Il Kim

IPC分类号： H01L2144

CPC分类号： H05K1/021 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K1/056 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/0097 ,  H05K3/321 ,  H05K3/4644 ,  H05K2203/0315 ,  H05K2203/049 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00

摘要： A printed circuit board (PCB) with a heat dissipation element, a method for manufacturing the PCB, and a semiconductor package using the PCB dissipates heat generated from the semiconductor chip and reduces a printed circuit board height. The PCB includes a heat sink panel, an alloy panel attached to one surface of the heat sink panel serving to ground and to dissipate heat, a circuit pattern layer having via holes formed on one surface of the alloy panel and electrically coupled to the alloy panel, and a cavity formed by perforating the circuit pattern layer and the alloy panel. A semiconductor chip is on the heat sink panel in the cavity and electrically coupled to the circuit pattern layer. The alloy panels with the circuit patterns can be manufactured in pairs with an insulation carrier therebetween. A plurality of dissipation protrusions can be formed on the surface of the alloy panel or the surface of the heat sink panel to couple the same.

摘要翻译： 具有散热元件的印刷电路板（PCB），PCB的制造方法以及使用该PCB的半导体封装消耗了半导体芯片产生的热量并降低了印刷电路板的高度。 PCB包括散热面板，附接到用于接地并散热的散热板的一个表面的合金面板，具有形成在合金面板的一个表面上并且电耦合到合金面板的通孔的电路图案层 以及通过对电路图案层和合金面板进行穿孔而形成的空腔。 半导体芯片位于空腔中的散热板上并电耦合到电路图案层。 具有电路图案的合金面板可以与它们之间的绝缘载体成对地制造。 可以在合金面板的表面或散热面板的表面上形成多个耗散突起，以将其连接。

公开(公告)号：US06509634B1

公开(公告)日：2003-01-21

申请号：US09667008

申请日：2000-09-21

申请人： Sung-Gue Lee ,  Yong-Il Kim

发明人： Sung-Gue Lee ,  Yong-Il Kim

IPC分类号： H01L2302

CPC分类号： H01L24/83 ,  H01L24/28 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K1/0287 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/10287 ,  H05K2201/10674

摘要： A chip mounting structure provides an adhesive conductor between a chip and a printed circuit board. The adhesive conductor includes an adhesive layer having viscoelasticity to cushion thermal shock caused due to a difference in the thermal expansive coefficients between mutually connected layers; and conductive wires for electrically connecting the layers by vertically penetrating the adhesive layer. The adhesive conductor in accordance with the present invention includes a plurality of conductive wires penetrating the adhesive layer having viscoelasticity in a half-hardened state, so that the chip and the printed circuit board can be physically attached and at the same time be electrically connected. Also, the flip chip structure is protected from the thermal shock caused due to the difference between the thermal expansive coefficients of the chip and the printed circuit board, so that products fabricated by adopting it can have a high reliability.

摘要翻译： 芯片安装结构在芯片和印刷电路板之间提供粘合导体。 粘合导体包括具有粘弹性的粘合剂层，以缓冲由于相互连接的层之间的热膨胀系数的差异引起的热冲击; 以及用于通过垂直地穿透粘合剂层来电连接层的导线。 根据本发明的粘合导体包括穿过具有半硬化状态的粘弹性的粘合剂层的多个导电丝，使得芯片和印刷电路板可以物理地附接并且同时电连接。 此外，由于芯片和印刷电路板的热膨胀系数之间的差异导致的倒装芯片结构受到保护，使得通过采用它制造的产品可以具有高的可靠性。

公开(公告)号：US08426739B2

公开(公告)日：2013-04-23

申请号：US12745667

申请日：2008-12-01

申请人： Kwang Tae Lee ,  Sung Gue Lee ,  Jae Bong Choi

发明人： Kwang Tae Lee ,  Sung Gue Lee ,  Jae Bong Choi

IPC分类号： H05K1/03

CPC分类号： H05K3/0097 ,  H05K1/0271 ,  H05K3/0052 ,  H05K2201/09354 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/2009 ,  H05K2203/0169

摘要： Disclosed is a printed circuit board including an insulation member on which a first region and a second region are defined, a circuit pattern formed on the first region, and a support member formed on the second region.

摘要翻译： 公开了一种印刷电路板，包括：绝缘部件，其上限定有第一区域和第二区域;形成在第一区域上的电路图案;以及形成在第二区域上的支撑部件。

公开(公告)号：US07320173B2

公开(公告)日：2008-01-22

申请号：US10769885

申请日：2004-02-03

申请人： Sung-Gue Lee ,  Jung-Ho Hwang ,  Joon-Wook Han ,  Sang-Min Lee ,  Tae-Sik Eo ,  Yu-Seock Yang

发明人： Sung-Gue Lee ,  Jung-Ho Hwang ,  Joon-Wook Han ,  Sang-Min Lee ,  Tae-Sik Eo ,  Yu-Seock Yang

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K3/423 ,  H05K3/0023 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0346 ,  H05K2203/0577 ,  H05K2203/0733 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method for fabricating a multi-layer printed circuit board can include forming an etching resist layer on a first metal layer having plating grooves that selectively expose the first metal layer, forming a plated layer at the surface of the first metal layer exposed by the plating groove through a plating process to form connection protrusion, removing the etching resist layer, forming an insulation layer at the first metal layer and positioning a second metal layer at the surface of the insulation layer coupled to an end portion of the connection protrusion. By forming the connection protrusion through the plating process, a loss of material can be reduced and a strength of the connection protrusion can be increased. Further, a complexity of the fabrication process is reduced to reduce costs and increase productivity.

摘要翻译： 制造多层印刷电路板的方法可以包括在具有选择性地暴露第一金属层的镀槽的第一金属层上形成抗蚀剂层，在由电镀暴露的第一金属层的表面形成镀层 通过电镀工艺形成连接突起，去除抗蚀剂层，在第一金属层处形成绝缘层，并将第二金属层定位在连接到连接突起的端部的绝缘层的表面处。 通过通过电镀工艺形成连接突起，可以减少材料的损失，并且可以提高连接突起的强度。 此外，减少制造过程的复杂性以降低成本并提高生产率。

公开(公告)号：US07189302B2

公开(公告)日：2007-03-13

申请号：US10981778

申请日：2004-11-05

申请人： Jung-Ho Hwang ,  Sung-Gue Lee ,  Sang-Min Lee ,  Joon-Wook Han ,  Tae-Sik Eo ,  Yu-Seock Yang

发明人： Jung-Ho Hwang ,  Sung-Gue Lee ,  Sang-Min Lee ,  Joon-Wook Han ,  Tae-Sik Eo ,  Yu-Seock Yang

IPC分类号： C25D11/08 ,  C25D5/02 ,  B29C65/00

CPC分类号： H05K3/4647 ,  H05K3/0097 ,  H05K3/423 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09845 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K2203/1536 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A fabricating method for a multi-layer printed circuit board is provided. The method may include attaching a releasing film at upper and lower surfaces of a center layer and attaching a first metal film to each of the releasing films and a resist layer to each of the first metal films to form a base member. A first connection portion may then be formed on each of the first metal films, and a second connection portion may be integrally formed on each of the first connection portions. A second metal film may then be formed on each of the second connection portions so as to be electrically connected to the connection portions, and, in turn, to the first metal films. Specific portions of the second metal films may be etched to form copper patterns. Upper and lower portions may then be separated by the releasing films to form separate multi-layer printed circuit boards.

摘要翻译： 提供了一种用于多层印刷电路板的制造方法。 该方法可以包括在中心层的上表面和下表面处附接释放膜并将第一金属膜附接到每个释放膜和将抗蚀剂层附接到每个第一金属膜以形成基底部件。 然后可以在每个第一金属膜上形成第一连接部分，并且第二连接部分可以一体地形成在每个第一连接部分上。 然后可以在每个第二连接部分上形成第二金属膜，以便电连接到连接部分，并且依次连接到第一金属膜。 可以蚀刻第二金属膜的特定部分以形成铜图案。 然后可以通过释放膜分离上部和下部以形成单独的多层印刷电路板。

公开(公告)号：US07098533B2

公开(公告)日：2006-08-29

申请号：US10934556

申请日：2004-09-07

申请人： Sung Gue Lee ,  Yong Il Kim

发明人： Sung Gue Lee ,  Yong Il Kim

IPC分类号： H01L23/10 ,  H01L23/34 ,  H01L23/043 ,  H01L23/495 ,  H01L31/024

CPC分类号： H05K1/021 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K1/056 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/0097 ,  H05K3/321 ,  H05K3/4644 ,  H05K2203/0315 ,  H05K2203/049 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00

摘要： A printed circuit board (PCB) with a heat dissipation element, a method for manufacturing the PCB, and a semiconductor package using the PCB dissipates heat generated from the semiconductor chip and reduces a printed circuit board height. The PCB includes a heat sink panel, an alloy panel attached to one surface of the heat sink panel serving to ground and to dissipate heat, a circuit pattern layer having via holes formed on one surface of the alloy panel and electrically coupled to the alloy panel, and a cavity formed by perforating the circuit pattern layer and the alloy panel. A semiconductor chip is on the heat sink panel in the cavity and electrically coupled to the circuit pattern layer. The alloy panels with the circuit patterns can be manufactured in pairs with an insulation carrier therebetween. A plurality of dissipation protrusions can be formed on the surface of the alloy panel or the surface of the heat sink panel to couple the same.

摘要翻译： 具有散热元件的印刷电路板（PCB），PCB的制造方法以及使用该PCB的半导体封装消耗了半导体芯片产生的热量并降低了印刷电路板的高度。 PCB包括散热面板，附接到用于接地并散热的散热板的一个表面的合金面板，具有形成在合金面板的一个表面上并且电耦合到合金面板的通孔的电路图案层 以及通过对电路图案层和合金面板进行穿孔而形成的空腔。 半导体芯片位于空腔中的散热板上并电耦合到电路图案层。 具有电路图案的合金面板可以与它们之间的绝缘载体成对地制造。 可以在合金面板的表面或散热面板的表面上形成多个耗散突起，以将其连接。

公开(公告)号：US07049178B2

公开(公告)日：2006-05-23

申请号：US10743302

申请日：2003-12-23

申请人： Yong Il Kim ,  Sung Gue Lee ,  Yu Seock Yang

发明人： Yong Il Kim ,  Sung Gue Lee ,  Yu Seock Yang

IPC分类号： H01L21/44 ,  H01L21/58 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L21/4857 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of fabricating a semiconductor package is disclosed in which a first Ni—Au plating is formed on a bonding pad for connection with a semiconductor chip, without a mechanical process or a masking operation. The method applies a copper plating on a through bore and the bonding pad, where the copper plated layer formed on the bonding pad is selectively removed, and then a second Ni—Au plating is formed on the bonding pad and a ball pad.