公开(公告)号：US20120043656A1

公开(公告)日：2012-02-23

申请号：US13289593

申请日：2011-11-04

申请人： Yoshinari HAYASHI

发明人： Yoshinari HAYASHI

IPC分类号： H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L24/02 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/094 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

摘要翻译： 半导体器件的安装可靠性得到改善。 半导体芯片安装在布线基板的上表面上。 多个焊球分别设置在形成在布线基板的下表面上的多个焊盘上。 多个焊盘包括沿着布线基板的下表面的周边部分布置成多行并布置的第一焊盘组，以及布置在布线基板的下表面中的第一焊盘组内部的第二焊盘组。 第一接地组中的焊盘以第一间距布置，并且第二接地组中的焊盘以比第一间距高的第二间距布置。

公开(公告)号：US20080083978A1

公开(公告)日：2008-04-10

申请号：US11946581

申请日：2007-11-28

申请人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

发明人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

IPC分类号： H01L23/488

CPC分类号： H01L23/49816 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device having a first semiconductor chip with an SDRAM and a second semiconductor chip with a an MPU controlling the SDRAM. The contour size of the semiconductor device is reduced to a smaller size without impairing the testability of the first semiconductor chip. The two semiconductor chips are stacked over the top surface of an interconnect substrate and sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

摘要翻译： 具有SDRAM的第一半导体芯片和具有控制SDRAM的MPU的第二半导体芯片的半导体器件。 半导体器件的轮廓尺寸减小到更小的尺寸，而不损害第一半导体芯片的可测试性。 将两个半导体芯片堆叠在互连基板的顶表面上并密封在模制树脂中，从而形成SiP（系统级封装）。 与第二芯片电连接的第一端子被布置为在互连基板的底表面的外周上的SiP的外部端子。 电连接两个芯片的互连电连接的多个第二电极被安装作为用于测试SDRAM的端子。 第二电极比互连基板的底表面上的第一外部电极的最内排更向内定位。

公开(公告)号：US08405231B2

公开(公告)日：2013-03-26

申请号：US13289593

申请日：2011-11-04

申请人： Yoshinari Hayashi

发明人： Yoshinari Hayashi

IPC分类号： H01L23/42 ,  H01L23/58

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L24/02 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/094 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

摘要翻译： 半导体器件的安装可靠性得到改善。 半导体芯片安装在布线基板的上表面上。 多个焊球分别设置在形成在布线基板的下表面上的多个焊盘之上。 多个焊盘包括沿着布线基板的下表面的周边部分布置成多行并布置的第一焊盘组，以及布置在布线基板的下表面中的第一焊盘组内部的第二焊盘区域。 第一接地组中的焊盘以第一间距布置，并且第二接地组中的焊盘以比第一间距高的第二间距布置。

公开(公告)号：US08076787B2

公开(公告)日：2011-12-13

申请号：US12549718

申请日：2009-08-28

申请人： Yoshinari Hayashi

发明人： Yoshinari Hayashi

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L24/02 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/094 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

摘要翻译： 半导体器件的安装可靠性得到改善。 半导体芯片安装在布线基板的上表面上。 多个焊球分别设置在形成在布线基板的下表面上的多个焊盘上。 多个焊盘包括沿着布线基板的下表面的周边部分布置成多行并布置的第一焊盘组，以及布置在布线基板的下表面中的第一焊盘组内部的第二焊盘组。 第一接地组中的焊盘以第一间距布置，并且第二接地组中的焊盘以比第一间距高的第二间距布置。

公开(公告)号：US20100090333A1

公开(公告)日：2010-04-15

申请号：US12549718

申请日：2009-08-28

申请人： Yoshinari HAYASHI

发明人： Yoshinari HAYASHI

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L24/02 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/094 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

摘要翻译： 半导体器件的安装可靠性得到改善。 半导体芯片安装在布线基板的上表面上。 多个焊球分别设置在形成在布线基板的下表面上的多个焊盘上。 多个焊盘包括沿着布线基板的下表面的周边部分布置成多行并布置的第一焊盘组，以及布置在布线基板的下表面中的第一焊盘组内部的第二焊盘组。 第一接地组中的焊盘以第一间距布置，并且第二接地组中的焊盘以比第一间距高的第二间距布置。

公开(公告)号：US07652368B2

公开(公告)日：2010-01-26

申请号：US11946581

申请日：2007-11-28

申请人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

发明人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

IPC分类号： H01L21/58

CPC分类号： H01L23/49816 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device having a first semiconductor chip with an SDRAM and a second semiconductor chip with a an MPU controlling the SDRAM. The contour size of the semiconductor device is reduced to a smaller size without impairing the testability of the first semiconductor chip. The two semiconductor chips are stacked over the top surface of an interconnect substrate and sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

摘要翻译： 具有SDRAM的第一半导体芯片和具有控制SDRAM的MPU的第二半导体芯片的半导体器件。 半导体器件的轮廓尺寸减小到更小的尺寸，而不损害第一半导体芯片的可测试性。 将两个半导体芯片堆叠在互连基板的顶表面上并密封在模制树脂中，从而形成SiP（系统级封装）。 与第二芯片电连接的第一端子被布置为在互连基板的底表面的外周上的SiP的外部端子。 电连接两个芯片的互连电连接的多个第二电极被安装作为用于测试SDRAM的端子。 第二电极比互连基板的底表面上的第一外部电极的最内排更向内定位。

公开(公告)号：US07323773B2

公开(公告)日：2008-01-29

申请号：US11221904

申请日：2005-09-09

申请人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

发明人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

IPC分类号： H01L21/58

CPC分类号： H01L23/49816 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

摘要翻译： 公开了具有第一和第二半导体芯片的半导体器件。 第一半导体芯片具有存储电路。 第二半导体芯片具有控制存储电路的电路。 半导体器件的轮廓尺寸减小到客户所需的较小尺寸，而不损害具有存储电路的第一半导体芯片的可测试性。 控制存储电路的电路由MPU组成。 存储电路由SDRAM组成。 两个半导体芯片在互连衬底的顶表面上彼此堆叠。 将芯片密封在模制树脂中，从而形成SiP（系统级封装）。 与第二芯片电连接的第一端子被布置为在互连基板的底表面的外周上的SiP的外部端子。 电连接两个芯片的互连电连接的多个第二电极被安装作为用于测试SDRAM的端子。 第二电极比互连基板的底表面上的第一外部电极的最内排更向内定位。

公开(公告)号：US20060060959A1

公开(公告)日：2006-03-23

申请号：US11221904

申请日：2005-09-09

申请人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

发明人： Yoshinari Hayashi ,  Toshikazu Ishikawa ,  Takayuki Hoshino

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49816 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

摘要翻译： 公开了具有第一和第二半导体芯片的半导体器件。 第一半导体芯片具有存储电路。 第二半导体芯片具有控制存储电路的电路。 半导体器件的轮廓尺寸减小到客户所需的较小尺寸，而不损害具有存储电路的第一半导体芯片的可测试性。 控制存储电路的电路由MPU组成。 存储电路由SDRAM组成。 两个半导体芯片在互连衬底的顶表面上彼此堆叠。 将芯片密封在模制树脂中，从而形成SiP（系统级封装）。 与第二芯片电连接的第一端子被布置为在互连基板的底表面的外周上的SiP的外部端子。 电连接两个芯片的互连电连接的多个第二电极被安装作为用于测试SDRAM的端子。 第二电极比互连基板的底表面上的第一外部电极的最内排更向内定位。

公开(公告)号：US06836021B2

公开(公告)日：2004-12-28

申请号：US10698410

申请日：2003-11-03

申请人： Toshikazu Ishikawa ,  Takahiro Naito ,  Hiroshi Kuroda ,  Yoshinari Hayashi

发明人： Toshikazu Ishikawa ,  Takahiro Naito ,  Hiroshi Kuroda ,  Yoshinari Hayashi

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/00012 ,  H01L2924/207

摘要： A reduction in a size of a multichip module having a plurality of chips (higher-density mounting) and improvements in the reliability and functionality thereof are intended. By alternately repeating stacking in layers and processing of insulating films and conductive films, a microcomputer chip is face-down bonded to an upper portion of a wiring substrate having build-up substrate portions formed with wires with a surface of the microcomputer chip formed with a bump electrode facing downward. Memory chips are bonded onto an upper portion of the microcomputer chip with the respective surfaces thereof formed with bonding pads and the like facing upward. The bonding pads and the like are connected to bonding pads along edges of the wiring substrate with conductive wires. By thus disposing the microcomputer chip having multifunctionality and a larger number of terminals in a lower layer, the size reduction of a device and the like can be achieved.

摘要翻译： 旨在减少具有多个芯片（更高密度安装）的多芯片模块的尺寸以及其可靠性和功能性的改进。 通过交替重复层叠堆叠和处理绝缘膜和导电膜，微机芯片面向下接合到布线基板的上部，该布线基板具有形成有导线的堆积基板部分，微电脑芯片的表面形成有 凸块电极朝下。 存储芯片被结合到微计算机芯片的上部，其各个表面形成有面向上的接合焊盘等。 接合焊盘等通过导线与布线基板的边缘连接到焊盘。 通过这样将具有多功能的微型计算机芯片和更多的端子配置在下层中，可以实现装置的尺寸减小等。