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公开(公告)号：US20210267044A1
公开(公告)日：2021-08-26
申请号：US17249084
申请日：2021-02-19
摘要： A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A component is embedded in the stack. A first thermally conductive block is located above and thermally connected with the component, and a second thermally conductive block is located below and thermally coupled with the component. Heat generated by the component during operation is removed via at least one of the first thermally conductive block and the second thermally conductive block.
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公开(公告)号：US09750134B2
公开(公告)日：2017-08-29
申请号：US14773201
申请日：2014-03-05
IPC分类号： H05K1/03 , H05K1/02 , H05K3/46 , H05K1/09 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/10 , H05K3/42
CPC分类号： H05K1/0298 , H05K1/028 , H05K1/09 , H05K1/115 , H05K1/162 , H05K3/0047 , H05K3/10 , H05K3/429 , H05K3/4611 , H05K3/4682 , H05K3/4691 , H05K3/4694 , H05K2201/0355 , H05K2201/096 , H05K2203/061 , H05K2203/063
摘要： A method for producing a printed circuit board (13, 15, 16) with multilayer subareas in sections, characterized by the following steps: a) providing at least one conducting foil (1, 1′) and application of a dielectric insulating foil (3, 3′) to at least one subarea of the conducting foil; b) applying a structure of conducting paths (4, 4′) to the insulating layer (3, 3′); c) providing one further printed circuit board structure; d) joining of the further printed circuit board structure with the conducting foil (1, 1′) plus insulating layer (3, 3′) and conducting paths (4, 4′) by interposing a prepreg layer (5, 85; 18, 18′), and e) laminating the parts joined in step d) under pressing pressure and heat; and a printed circuit board produced according to this method.
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公开(公告)号：US10720405B2
公开(公告)日：2020-07-21
申请号：US16092917
申请日：2017-04-07
发明人： Heinz Moitzi , Dietmar Drofenik
IPC分类号： H01L23/31 , H01L23/49 , H01L23/00 , H01L21/56 , H01L21/683 , H01L23/538 , H01L21/48 , H01L23/498
摘要： A semifinished product includes a base structure, wafer structures, a cover structure and a further cover structure. The base structure has an electrically conductive layer and/or an electrically insulating layer. The wafer structures are on the base structure and have electronic components. The cover structure has at least one further layer and covers the wafer structures and part of the base structure. Separate electronic components are arranged on the cover structure and a further cover structure is provided to cover the separate electronic components and part of the cover structure. A component carrier includes a bare die with pads. The bare die is laminated between a base laminate and a cover laminate and has a lateral semiconductor surface being exposed from the base laminate and the cover laminate. A redistribution layer increases spacing of external electric contacts relative to spacing between pads of the bare die.
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公开(公告)号：US20190157242A1
公开(公告)日：2019-05-23
申请号：US16092917
申请日：2017-04-07
发明人： Heinz Moitzi , Dietmar Drofenik
IPC分类号： H01L23/00 , H01L21/48 , H01L21/683 , H01L23/31 , H01L21/56 , H01L23/498
CPC分类号： H01L24/97 , H01L21/4857 , H01L21/486 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49822 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/19 , H01L24/20 , H01L24/94 , H01L2221/68345 , H01L2221/68359 , H01L2221/68372 , H01L2224/0231 , H01L2224/02371 , H01L2224/02379 , H01L2224/03002 , H01L2224/04042 , H01L2224/04105 , H01L2224/05548 , H01L2224/06181 , H01L2224/08225 , H01L2224/211 , H01L2224/2518 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2224/95001 , H01L2924/14 , H01L2924/1427 , H01L2924/1431 , H01L2924/1434 , H01L2924/3025 , H01L2924/3511 , H01L2924/00014 , H01L2224/023 , H01L2924/00012
摘要： A method of manufacturing a batch of component carriers is disclosed. The method includes providing a plurality of separate wafer structures, each comprising a plurality of electronic components, simultaneously laminating the wafer structures with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and singularizing a structure resulting from the laminating into the plurality of component carriers, each comprising at least one of the electronic components, a part of the at least one electrically conductive layer structure and a part of the at least one electrically insulating layer structure.
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公开(公告)号：US09980380B2
公开(公告)日：2018-05-22
申请号：US15331987
申请日：2016-10-24
CPC分类号： H05K1/142 , H05K1/115 , H05K1/185 , H05K1/189 , H05K3/225 , H05K3/368 , H05K3/4691 , H05K3/4694 , H05K2201/0187 , H05K2201/09163 , H05K2201/09845 , H05K2203/1461 , Y10T29/49155
摘要： In a method for producing a printed circuit board consisting of at least two printed circuit regions, wherein the printed circuit board regions each compromise at least one conductive layer and/or at least one device or once conductive component, wherein printed circuit board regions to be connected to another one, in the region of in each case at least one lateral surface directly adjoining one another, are connected to one another by a coupling or connection, and wherein, after a coupling or connection of printed circuit board regions, at least one additional layer or ply of the printed circuit board is applied over the printed circuit board regions, the additional layer is embodied as a conductive layer, which is contact-connected via plated-through holes to conductive layers or devices or components integrated in the printed circuit board regions.
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公开(公告)号：US11523496B2
公开(公告)日：2022-12-06
申请号：US17249084
申请日：2021-02-19
摘要： A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A component is embedded in the stack. A first thermally conductive block is located above and thermally connected with the component, and a second thermally conductive block is located below and thermally coupled with the component. Heat generated by the component during operation is removed via at least one of the first thermally conductive block and the second thermally conductive block.
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公开(公告)号：US11380650B2
公开(公告)日：2022-07-05
申请号：US15929291
申请日：2020-04-23
发明人： Heinz Moitzi , Dietmar Drofenik
IPC分类号： H01L23/00 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/538 , H01L21/48 , H01L23/498
摘要： A method of manufacturing a batch of component carriers is disclosed. The method includes providing a plurality of separate wafer structures, each comprising a plurality of electronic components, simultaneously laminating the wafer structures with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and singularizing a structure resulting from the laminating into the plurality of component carriers, each comprising at least one of the electronic components, a part of the at least one electrically conductive layer structure and a part of the at least one electrically insulating layer structure.
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