公开(公告)号：US08110930B2

公开(公告)日：2012-02-07

申请号：US11820454

申请日：2007-06-19

申请人： Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew ,  Bok Eng Cheah

发明人： Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew ,  Bok Eng Cheah

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81232 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

摘要： Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.

摘要翻译： 描述了用于为堆叠的管芯封装提供模具背面金属化和/或表面活化粘合的方法和装置。 在一个实施例中，第一管芯的有源金属层可以通过第二管芯的硅通孔和/或管芯背侧金属化层耦合到第二管芯的有源金属层。 还描述了其它实施例。

公开(公告)号：US20140091442A1

公开(公告)日：2014-04-03

申请号：US13631392

申请日：2012-09-28

申请人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

发明人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2924/207

摘要： An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

摘要翻译： 一种包括具有装置侧的模具的装置; 以及堆积载体，其包括主体，所述主体包括设置在所述管芯的器件侧上的导电材料和介电材料的多个交替层，被构图成多个焊盘或焊盘的极限导电层; 以及栅格阵列，其包括设置在所述主体的所述极限导电层的所述多个焊盘中的相应的一个焊盘上的多个导电柱，所述柱中的至少一个通过至少一个 身体导电材料的一部分。 一种包括形成包括模具的堆积载体的主体的方法，所述积聚载体的主体包括极限导电层，并且在主体的最终导电层上形成包括多个导电柱的栅格阵列。

公开(公告)号：US08198716B2

公开(公告)日：2012-06-12

申请号：US11728534

申请日：2007-03-26

申请人： Shanggar Periaman ,  Kooi Chi Ooi ,  Bok Eng Cheah ,  Yen Hsiang Chew

发明人： Shanggar Periaman ,  Kooi Chi Ooi ,  Bok Eng Cheah ,  Yen Hsiang Chew

IPC分类号： H01L23/48

CPC分类号： H01L25/18 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods and apparatus to provide die backside connections are described. In one embodiment, the backside of a die is metallized and coupled to another die or a substrate. Other embodiments are also described.

摘要翻译： 描述提供模背侧连接的方法和装置。 在一个实施例中，管芯的背面被金属化并且耦合到另一个管芯或衬底。 还描述了其它实施例。

公开(公告)号：US07692278B2

公开(公告)日：2010-04-06

申请号：US11642293

申请日：2006-12-20

申请人： Shanggar Periaman ,  Kooi Chi Ooi ,  Bok Eng Cheah

发明人： Shanggar Periaman ,  Kooi Chi Ooi ,  Bok Eng Cheah

IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.

摘要翻译： 在一些实施例中，提供了一种装置和系统。 该装置和系统可以包括第一集成电路管芯，其包括多个硅通孔和耦合到多个硅通孔的第一表面激活的结合位置，以及第二集成电路管芯，其包括第二表面激活的结合部位， 表面活化粘结部位。 第一表面活化的粘合位点可以包括第一清洁金属，第二表面活化的粘结位点可以包括第二清洁金属。 如果第一表面活性键合位点与第二表面活化键合位点相连，则第一活化表面活化键合位点的相应金属原子扩散到第二表面活化键合位点，第二活化表面活化键合位点的相应金属原子扩散 进入第一表面活化粘结部位。

公开(公告)号：US20080315421A1

公开(公告)日：2008-12-25

申请号：US11820454

申请日：2007-06-19

申请人： Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew ,  Bok Eng Cheah

发明人： Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew ,  Bok Eng Cheah

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81232 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

摘要： Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.

摘要翻译： 描述了用于为堆叠的管芯封装提供模具背面金属化和/或表面活化粘合的方法和装置。 在一个实施例中，第一管芯的有源金属层可以通过第二管芯的硅通孔和/或管芯背侧金属化层耦合到第二管芯的有源金属层。 还描述了其它实施例。

公开(公告)号：US20080315388A1

公开(公告)日：2008-12-25

申请号：US11767318

申请日：2007-06-22

申请人： Shanggar Periaman ,  Bok Eng Cheah ,  Yen Hsiang Chew ,  Kooi Chi Ooi

发明人： Shanggar Periaman ,  Bok Eng Cheah ,  Yen Hsiang Chew ,  Kooi Chi Ooi

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L25/0652 ,  H01L24/81 ,  H01L2224/81232 ,  H01L2224/81801 ,  H01L2924/14 ,  H01L2924/00

摘要： In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit device coupled to the substrate and adjacent to one side of the substantially horizontal integrated circuit device. Other embodiments are also disclosed and claimed.

摘要翻译： 在一些实施例中，呈现用于3D处理器封装的垂直控制侧芯片连接。 在这方面，引入一种装置，该装置具有相对于基板的基本水平的基板，耦合到该基板的集成电路装置，以及与基板相关的基本上垂直的集成电路装置， 到基本水平的集成电路器件的一侧。 还公开并要求保护其他实施例。

公开(公告)号：US09721878B2

公开(公告)日：2017-08-01

申请号：US13631392

申请日：2012-09-28

申请人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

发明人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2924/207

摘要： An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

公开(公告)号：US08987896B2

公开(公告)日：2015-03-24

申请号：US12890345

申请日：2010-09-24

申请人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

发明人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H05K1/185 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19106 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/183 ,  H05K3/10 ,  H05K3/34 ,  H05K3/36 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.

摘要翻译： 一种装置包括无芯安装基板和设置在无芯安装基板上的插入件，其具有设置在插入件中的凹部中的芯片和无芯基板。 该装置可以包括与插入器中的互连通道接触的封装间焊料凸块，以及包括顶部封装衬底和设置在顶部封装衬底上的顶部管芯的顶部芯片封装。 顶部封装衬底与封装间焊料凸块接触。

公开(公告)号：US20140175670A1

公开(公告)日：2014-06-26

申请号：US14190218

申请日：2014-02-26

申请人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

发明人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/16 ,  H01L24/31 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83894 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

摘要翻译： 描述了电子组件的形成。 一个实施例包括每个包括前侧和后侧的第一和第二半导体管芯结构，前侧包括有源区，背面包括金属区和非金属区。 第一和第二半导体管芯结构包括多个通孔，通孔在有源区和背侧金属区之间形成电连接。 第一和第二半导体管芯结构与第一半导体管芯结构的背侧上的金属区域中的至少一个与第二半导体管芯结构的背面上的金属区域中的至少一个直接接触而堆叠在一起。 描述和要求保护其他实施例。

公开(公告)号：US20120319293A1

公开(公告)日：2012-12-20

申请号：US13162799

申请日：2011-06-17

申请人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

发明人： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/76898 ,  H01L23/31 ,  H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A microelectronic device comprises a first surface (110, 710), a second surface (120, 720), and a passageway (130, 730) extending from the first surface to the second surface. The passageway contains a plurality of electrically conductive channels (131, 132, 231, 232) separated from each other by an electrically insulating material (133, 1133).

摘要翻译： 微电子器件包括第一表面（110,710），第二表面（120,720）和从第一表面延伸到第二表面的通道（130,730）。 通道包含通过电绝缘材料（133,1133）彼此分离的多个导电通道（131,132,231,232）。