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17 条记录 (耗时 0.026 秒)

    Phase Change Memory Cell with Vertical Transistor
    4.
    发明申请
    Phase Change Memory Cell with Vertical Transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US20090001337A1

    公开(公告)日：2009-01-01

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/336 ,  H01L21/06 ,  H01L29/02

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

    Method of TEM sample preparation for electron holography for semiconductor devices
    5.
    发明授权
    Method of TEM sample preparation for electron holography for semiconductor devices 失效
    半导体器件电子全息术的TEM样品制备方法

    公开(公告)号：US07560692B2

    公开(公告)日：2009-07-14

    申请号：US11617386

    申请日：2006-12-28

    申请人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

    发明人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

    IPC分类号： G01N1/32 ,  G01N23/04

    CPC分类号： G01N1/2806

    摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

    摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。

    Sidewall image transfer processes for forming multiple line-widths
    7.
    发明授权
    Sidewall image transfer processes for forming multiple line-widths 失效
    用于形成多个线宽的侧壁图像传输过程

    公开(公告)号：US07699996B2

    公开(公告)日：2010-04-20

    申请号：US11680204

    申请日：2007-02-28

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： H01B13/00

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

    摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD

    摘要翻译： 同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。 该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。 然后，对SIT层进行图案化，形成SIT区域。 然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。 然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。 所述图案化包括光刻工艺。 退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维度W2和第二维度W3，其中CD

    Phase change memory cell with vertical transistor
    8.
    发明授权
    Phase change memory cell with vertical transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US07932167B2

    公开(公告)日：2011-04-26

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/44

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

    SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS
    9.
    发明申请
    SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS 失效
    用于形成多个线宽的平面图像传输过程

    公开(公告)号：US20080206996A1

    公开(公告)日：2008-08-28

    申请号：US11680204

    申请日：2007-02-28

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

    摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD

    摘要翻译： 同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。 该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。 然后，对SIT层进行图案化，形成SIT区域。 然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。 然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。 所述图案化包括光刻工艺。 退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维W 2和第二维W 3，其中CD

    METHOD OF TEM SAMPLE PREPARATION FOR ELECTRON HOLOGRAPHY FOR SEMICONDUCTOR DEVICES
    10.
    发明申请
    METHOD OF TEM SAMPLE PREPARATION FOR ELECTRON HOLOGRAPHY FOR SEMICONDUCTOR DEVICES 失效
    用于半导体器件的电子照相的TEM样品制备方法

    公开(公告)号：US20080156987A1

    公开(公告)日：2008-07-03

    申请号：US11617386

    申请日：2006-12-28

    申请人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun Yu Wang

    发明人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun Yu Wang

    IPC分类号： G01N23/04

    CPC分类号： G01N1/2806

    摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

    摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并且减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。