公开(公告)号：US6117763A

公开(公告)日：2000-09-12

申请号：US939066

申请日：1997-09-29

Applicant: Charles May ,  Robin Cheung

Inventor： Charles May ,  Robin Cheung

IPC: H01L21/3105 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L23/5329 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/3121 ,  H01L21/31629 ,  H01L2924/0002 ,  Y10S438/906

Abstract: A method of making a semiconductor device includes forming a low permittivity dielectric layer over one or more conductive lines of a semiconductor device. The dielectric layer is made using a silicon-containing material having a relatively low permittivity including, for example, silicon oxyfluoride (SiO.sub.y F.sub.x) and hydrogen silsesquioxane (HSQ). An optional oxide layer may be formed over the dielectric layer. At least a portion of the dielectric layer and/or the optional oxide layer is subsequently removed to form a planar dielectric layer having a contaminated surface layer. The contaminated surface layer is due to exposure to water and is removed by, for example, exposing the surface to an acid, such as hydrofluoric acid.

Abstract translation: 制造半导体器件的方法包括在半导体器件的一个或多个导电线上形成低介电常数介电层。 电介质层使用包含例如氟氧化硅（SiO y F x）和氢倍半硅氧烷（HSQ））的具有较低介电常数的含硅材料制成。 可以在电介质层上形成任选的氧化物层。 随后去除介电层和/或任选的氧化物层的至少一部分以形成具有污染表面层的平面介电层。 受污染的表面层是由于暴露于水而被除去，例如通过使表面暴露于酸如氢氟酸。

公开(公告)号：US20120292585A1

公开(公告)日：2012-11-22

申请号：US13566584

申请日：2012-08-03

Applicant: Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

Inventor： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

IPC: H01L47/00 ,  H01L21/02

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

公开(公告)号：US08237142B2

公开(公告)日：2012-08-07

申请号：US12932642

申请日：2011-03-01

Applicant: Robin Cheung ,  Jonathan Bornstein ,  David Hansen ,  Travis Byonghyop Oh ,  Darrell Rinerson

Inventor： Robin Cheung ,  Jonathan Bornstein ,  David Hansen ,  Travis Byonghyop Oh ,  Darrell Rinerson

IPC: H01L29/02 ,  H01L29/06

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

公开(公告)号：US20060235563A1

公开(公告)日：2006-10-19

申请号：US11420916

申请日：2006-05-30

Applicant: Suketu Parikh ,  Robin Cheung

Inventor： Suketu Parikh ,  Robin Cheung

IPC: G06F19/00

CPC classification number: H01L22/20 ,  G05B19/4187 ,  G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32182 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/205 ,  Y02P90/22

Abstract: An apparatus for performing intra-tool monitoring and control within a multi-step processing system. The apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

Abstract translation: 一种用于在多步骤处理系统内执行工具内监视和控制的装置。 该设备提供位于多个半导体晶片处理工具中的每一个之间的计量站，使得可以在晶片从一个工具传递到提供内部工具监视的另一个工具时进行测量。 由计量站收集的数据耦合到度量数据分析器，该测量数据分析器确定是否应该调整多个晶片处理工具中的任何一个以改善整个晶片的处理。 因此，测量数据分析仪的输出提供控制参数以处理连接到半导体晶片处理系统内的每个工具的控制器连接的控制器。 因此，计量站和度量数据分析仪的操作提供前馈和反馈数据，以基于在计量站内收集的某些信息来控制工具。

公开(公告)号：US06635157B2

公开(公告)日：2003-10-21

申请号：US09867780

申请日：2001-05-29

Applicant: Yezdi Dordi ,  Donald J. Olgado ,  Ratson Morad ,  Peter Hey ,  Mark Denome ,  Michael Sugarman ,  Mark Lloyd ,  Joseph Stevens ,  Dan Marohl ,  Ho Seon Shin ,  Eugene Ravinovich ,  Robin Cheung ,  Ashok K. Sinha ,  Avi Tepman ,  Dan Carl ,  George Birkmaier

Inventor： Yezdi Dordi ,  Donald J. Olgado ,  Ratson Morad ,  Peter Hey ,  Mark Denome ,  Michael Sugarman ,  Mark Lloyd ,  Joseph Stevens ,  Dan Marohl ,  Ho Seon Shin ,  Eugene Ravinovich ,  Robin Cheung ,  Ashok K. Sinha ,  Avi Tepman ,  Dan Carl ,  George Birkmaier

IPC: C25D1700

CPC classification number: H01L21/6723 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06 ,  C25D21/02 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/67028 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67126 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67745 ,  H01L21/68707 ,  H01L21/68721 ,  H01L21/68728 ,  H01L21/68742 ,  H05K3/241

Abstract: The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.

公开(公告)号：US06436267B1

公开(公告)日：2002-08-20

申请号：US09650108

申请日：2000-08-29

Applicant: Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

Inventor： Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

IPC: C23C2802

CPC classification number: H01L21/2885 ,  H01L21/76877

Abstract: One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

Abstract translation: 本发明的一个方面提供一致的金属电镀技术，以在半导体衬底上形成亚微米高纵横比特征的无空隙金属互连。 本发明的一个实施方案提供了一种用于在基底上填充亚微米特征的方法，包括反应性预清洗基底，使用高密度等离子体物理气相沉积在基底上沉积阻挡层; 使用高密度等离子体物理气相沉积在阻挡层上沉积种子层; 以及使用高电阻电解质电化学沉积金属，并且在第一周期期间在第一沉积期间施加第一电流密度，然后施加第二电流密度。

公开(公告)号：US06319616B1

公开(公告)日：2001-11-20

申请号：US09430766

申请日：1999-10-29

Applicant: Sergey Lopatin ,  Robin Cheung

Inventor： Sergey Lopatin ,  Robin Cheung

IPC: B32B1504

CPC classification number: H01L21/76888 ,  H01L21/31687 ,  H01L21/76885 ,  Y10S257/915 ,  Y10S428/901 ,  Y10T428/12493 ,  Y10T428/12597 ,  Y10T428/12611

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide. An outer metal layer is formed over the seed layer metal oxide and the conductor

Abstract translation: 提供一种形成导线结构的方法。 在基板表面上形成粘合层。 种子层形成在粘合层上。 在种子层上形成导体以形成部分完整的结构。 部分完整的结构暴露于电解质并进行阳极氧化处理。 种子层和导体的一部分的至少一部分分别转化为晶种层金属氧化物和导体金属氧化物。 粘合层的至少一部分被转化为粘合层金属氧化物，并且导体的另一部分转变为导体金属氧化物。 在种子层金属氧化物和导体上形成外部金属层

公开(公告)号：US06276072B1

公开(公告)日：2001-08-21

申请号：US09396007

申请日：1999-09-15

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: F26B700

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism. The heating mechanism preferably comprises a heated substrate support adapted to support a substrate and to heat the supported substrate to a predetermined temperature, and the cooling mechanism preferably comprises a cooling plate. The transfer mechanism may comprise, for example, a wafer lift hoop having a plurality of fingers adapted to support a substrate, or a plurality of wafer lift pins. A dry gas source may be coupled to the chamber and adapted to supply a dry gas thereto. The chamber preferably includes a pump adapted to evacuate the chamber to a predetermined pressure during at least cooling. A method for heating and cooling a substrate also is provided.

Abstract translation: 提供了一种用于加热和冷却衬底的方法和装置。 提供了一种室，其包括适于加热位于加热机构附近的基板的加热机构，与加热机构间隔开并适于冷却位于冷却机构附近的基板的冷却机构，以及适于将基板 靠近加热机构的位置和靠近冷却机构的位置。 加热机构优选地包括适于支撑基板并将受支撑基板加热到预定温度的加热基板支撑件，并且冷却机构优选地包括冷却板。 转移机构可以包括例如具有适于支撑衬底的多个指状物的晶片提升环或多个晶片提升销。 干燥气源可以连接到室并适于向其供应干燥气体。 腔室优选地包括适于在至少冷却期间将腔室排空到预定压力的泵。 还提供了一种用于加热和冷却基板的方法。

公开(公告)号：US6124201A

公开(公告)日：2000-09-26

申请号：US097126

申请日：1998-06-12

Applicant: Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

Inventor： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76802

Abstract: An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. He stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.

Abstract translation: 具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。 在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。 通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。 第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。 第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。 他停止氮化物层是以矩形通孔结构蚀刻氮化物，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

公开(公告)号：US20140087073A1

公开(公告)日：2014-03-27

申请号：US14035567

申请日：2013-09-24

Applicant: Igor Constantin Ivanov ,  Robin Cheung

Inventor： Igor Constantin Ivanov ,  Robin Cheung

IPC: B05C9/06 ,  B05D1/38

CPC classification number: B05C9/06 ,  B05D1/38 ,  H01L21/67017 ,  H01L21/67126

Abstract: In various exemplary embodiments, a system and related method for processing substrates is provided. In one embodiment, a substrate processing system is provided that includes a substrate load module, a plurality of facilities modules, a plurality of process chambers, a substrate transfer module, at least one transfer gate to provide a contamination barrier between various ones of adjacent modules, and at least one gas impermeable shell to provide a controlled atmosphere within the substrate processing system.

Abstract translation: 在各种示例性实施例中，提供了一种用于处理基板的系统和相关方法。 在一个实施例中，提供了一种衬底处理系统，其包括衬底加载模块，多个设施模块，多个处理室，衬底转移模块，至少一个传输门，以在各个相邻模块之间提供污染屏障 ，以及至少一个气体不可渗透的外壳，以在基板处理系统内提供受控的气氛。