公开(公告)号：US06923045B2

公开(公告)日：2005-08-02

申请号：US10892048

申请日：2004-07-15

申请人： Chee Peng Neo ,  Cher Khng Victor Tan ,  Kian Seng Ho ,  Hock Chuan Tan

发明人： Chee Peng Neo ,  Cher Khng Victor Tan ,  Kian Seng Ho ,  Hock Chuan Tan

IPC分类号： G01B11/30 ,  G01B5/34 ,  H01L21/66

CPC分类号： G01B11/303 ,  Y10T29/49004

摘要： An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.

摘要翻译： 一种用于检测微电子衬底特性的装置和方法。 微电子衬底可以具有第一表面，其具有第一形貌特征，诸如粗糙元件，以及与第一表面相对的第二表面，并且具有第二形貌特征，例如突出的导电结构。 在一个实施例中，该装置可以包括被配置为承载微电子基板的支撑构件，其中第一表面的第一部分被暴露并且第二表面的第二部分被暴露。 该装置还可以包括位于支撑构件附近并与微电子衬底的第一表面的第一部分对准的形貌特征检测器，以检测第一表面的特性，例如粗糙度，而微电子衬底由支撑体承载 会员。

公开(公告)号：US07213447B2

公开(公告)日：2007-05-08

申请号：US11157338

申请日：2005-06-20

申请人： Chee Peng Neo ,  Cher Khng Victor Tan ,  Kian Seng Ho ,  Hock Chuan Tan

发明人： Chee Peng Neo ,  Cher Khng Victor Tan ,  Kian Seng Ho ,  Hock Chuan Tan

IPC分类号： G01B5/34 ,  G06K9/00

CPC分类号： G01B11/303 ,  Y10T29/49004

摘要： An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.

摘要翻译： 一种用于检测微电子衬底特性的装置和方法。 微电子衬底可以具有第一表面，其具有第一形貌特征，诸如粗糙元件，以及与第一表面相对的第二表面，并且具有第二形貌特征，例如突出的导电结构。 在一个实施例中，该装置可以包括被配置为承载微电子基板的支撑构件，其中第一表面的第一部分被暴露并且第二表面的第二部分被暴露。 该装置还可以包括位于支撑构件附近并与微电子衬底的第一表面的第一部分对准的形貌特征检测器，以检测第一表面的特性，例如粗糙度，而微电子衬底由支撑体承载 会员。

公开(公告)号：US06779386B2

公开(公告)日：2004-08-24

申请号：US09944247

申请日：2001-08-30

申请人： Chee Peng Neo ,  Cher Khng Victor Tan ,  Kian Seng Ho ,  Hock Chuan Tan

发明人： Chee Peng Neo ,  Cher Khng Victor Tan ,  Kian Seng Ho ,  Hock Chuan Tan

IPC分类号： G01B534

CPC分类号： G01B11/303 ,  Y10T29/49004

摘要： An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.

摘要翻译： 一种用于检测微电子衬底特性的装置和方法。 微电子衬底可以具有第一表面，其具有第一形貌特征，诸如粗糙元件，以及与第一表面相对的第二表面，并且具有第二形貌特征，例如突出的导电结构。 在一个实施例中，该装置可以包括被配置为承载微电子基板的支撑构件，其中第一表面的第一部分被暴露并且第二表面的第二部分被暴露。 该装置还可以包括位于支撑构件附近并与微电子衬底的第一表面的第一部分对准的形貌特征检测器，以检测第一表面的特性，例如粗糙度，而微电子衬底由支撑体承载 会员。

公开(公告)号：US07368391B2

公开(公告)日：2008-05-06

申请号：US11215628

申请日：2005-08-29

申请人： Cher Khng Victor Tan ,  Choon Kuan Lee ,  Kian Chai Lee ,  Guek Har Lim ,  Wuu Yean Tay ,  Teck Huat Poh ,  Cheng Pour Poh

发明人： Cher Khng Victor Tan ,  Choon Kuan Lee ,  Kian Chai Lee ,  Guek Har Lim ,  Wuu Yean Tay ,  Teck Huat Poh ,  Cheng Pour Poh

IPC分类号： H01L21/311

CPC分类号： H01L24/97 ,  B33Y80/00 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/85385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H05K3/305 ,  H05K2201/09036 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The method may also include configuring the carrier substrate to include one or more recessed areas that laterally surround at least a portion of the die-attach location to receive excess adhesive.

摘要翻译： 一种用于设计载体基板的方法包括：配置至少一个管芯附着位置和从载体衬底的表面突出的一个或多个端子，以防止粘合剂材料污染其连接表面。 该方法还可以包括配置载体衬底以包括一个或多个凹陷区域，该凹陷区域横向围绕裸片附接位置的至少一部分以接收多余的粘合剂。

公开(公告)号：US07230330B2

公开(公告)日：2007-06-12

申请号：US10933060

申请日：2004-09-01

申请人： Teck Kheng Lee ,  Cher Khng Victor Tan

发明人： Teck Kheng Lee ,  Cher Khng Victor Tan

IPC分类号： H01L21/469

CPC分类号： H05K3/3436 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16237 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0394 ,  H05K2201/09472 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.

摘要翻译： 与半导体组件相关的装置和方法。 半导体组件包括可由诸如聚酰亚胺胶带的柔性材料构成的插入件。 布置在插入件的第一表面上的导电迹线的图案与附接到第一表面的半导体管芯电连通。 在相对的第二表面上可接近的互连凹部暴露一个或多个导电迹线。 基本上布置在互连凹槽内的诸如焊球的导电元件允许组件安装在基板或类似组件上。 通过在互连凹槽内基本上包含导电元件，完成组件的高度减小。 组件可以堆叠形成多组件。 互连结构，例如连接焊盘或第一表面上的放大迹线被用于连接堆叠的组件。

公开(公告)号：US06787923B2

公开(公告)日：2004-09-07

申请号：US10120169

申请日：2002-04-10

申请人： Cher Khng Victor Tan ,  Choon Kuan Lee ,  Kian Chai Lee ,  Guek Har Lim ,  Wuu Yean Tay ,  Teck Huat Poh ,  Cheng Pour Poh

发明人： Cher Khng Victor Tan ,  Choon Kuan Lee ,  Kian Chai Lee ,  Guek Har Lim ,  Wuu Yean Tay ,  Teck Huat Poh ,  Cheng Pour Poh

IPC分类号： H01L2348

CPC分类号： H01L24/83 ,  B33Y80/00 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/538 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/305 ,  H05K3/3452 ,  H05K2201/09036 ,  H05K2201/09909 ,  H05K2201/10689 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.

摘要翻译： 载体基板包括至少一个管芯附着位置和从载体衬底的表面突出的一个或多个端子，以防止粘合剂材料污染其连接表面。 用于载体衬底的焊接掩模包括可位于载体衬底的管芯支撑位置的至少一部分上的器件固定区域。 焊料掩模的大坝位于横向邻近于载体衬底的相应端子的周边的至少一部分。 载体基板和焊接掩模可以各自包括一个或多个凹陷区域，其分别横向包围其管芯附接位置和装置固定区域的至少一部分，以容纳一些多余的粘合剂。 还公开了包括载体基板和焊接掩模中的一个或两个的组件和封装，以及用于设计载体衬底和焊接掩模的组装方法和方法。

公开(公告)号：US07569473B2

公开(公告)日：2009-08-04

申请号：US11760458

申请日：2007-06-08

申请人： Teck Kheng Lee ,  Cher Khng Victor Tan

发明人： Teck Kheng Lee ,  Cher Khng Victor Tan

IPC分类号： H01L29/20

CPC分类号： H05K3/3436 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16237 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0394 ,  H05K2201/09472 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Apparatus and methods are disclosed relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.

摘要翻译： 公开了与半导体组件相关的装置和方法。 半导体组件包括可由诸如聚酰亚胺胶带的柔性材料构成的插入件。 布置在插入件的第一表面上的导电迹线的图案与附接到第一表面的半导体管芯电连通。 在相对的第二表面上可接近的互连凹部暴露一个或多个导电迹线。 基本上布置在互连凹槽内的诸如焊球的导电元件允许组件安装在基板或类似组件上。 通过在互连凹槽内基本上包含导电元件，完成组件的高度减小。 组件可以堆叠形成多组件。 互连结构，例如连接焊盘或第一表面上的放大迹线被用于连接堆叠的组件。

公开(公告)号：US07112520B2

公开(公告)日：2006-09-26

申请号：US10150516

申请日：2002-05-17

申请人： Teck Kheng Lee ,  Cher Khng Victor Tan

发明人： Teck Kheng Lee ,  Cher Khng Victor Tan

IPC分类号： H01L21/44

CPC分类号： H05K3/3436 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16237 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0394 ,  H05K2201/09472 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.

摘要翻译： 与半导体组件相关的装置和方法。 半导体组件包括可以由诸如聚酰亚胺胶带的柔性材料构成的插入件。 布置在插入件的第一表面上的导电迹线的图案与附接到第一表面的半导体管芯电连通。 在相对的第二表面上可接近的互连凹部暴露一个或多个导电迹线。 基本上布置在互连凹槽内的诸如焊球的导电元件允许组件安装在基板或类似组件上。 通过在互连凹槽内基本上包含导电元件，完成组件的高度减小。 组件可以堆叠形成多组件。 互连结构，例如连接焊盘或第一表面上的放大迹线被用于连接堆叠的组件。

公开(公告)号：US07061124B2

公开(公告)日：2006-06-13

申请号：US10936304

申请日：2004-09-07

申请人： Cher Khng Victor Tan ,  Choon Kuan Lee ,  Kian Chai Lee ,  Guek Har Lim ,  Wuu Yean Tay ,  Teck Huat Poh ,  Cheng Poh Pour

发明人： Cher Khng Victor Tan ,  Choon Kuan Lee ,  Kian Chai Lee ,  Guek Har Lim ,  Wuu Yean Tay ,  Teck Huat Poh ,  Cheng Poh Pour

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/83 ,  B33Y80/00 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/538 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/305 ,  H05K3/3452 ,  H05K2201/09036 ,  H05K2201/09909 ,  H05K2201/10689 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The solder may be positioned or formed on the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive excess adhesive.

摘要翻译： 用于载体衬底的焊接掩模包括可位于载体衬底的管芯支撑位置的至少一部分上的器件固定区域。 焊料掩模的大坝位于横向邻近于载体衬底的相应端子的周边的至少一部分。 载体基板包括至少一个管芯附着位置和从载体衬底的表面突出的一个或多个端子，以防止粘合剂材料污染其连接表面。 焊接掩模可以定位或形成在载体基板上。 载体衬底和焊料掩模可以各自包括一个或多个凹陷区域，其分别横向包围其管芯附接位置和器件固定区域的至少一部分，以容纳多余的粘合剂。

公开(公告)号：US07754531B2

公开(公告)日：2010-07-13

申请号：US11600665

申请日：2006-11-15

申请人： Wuu Yean Tay ,  Cher Khng Victor Tan

发明人： Wuu Yean Tay ,  Cher Khng Victor Tan

IPC分类号： H01L21/48 ,  H01L23/48 ,  H01L43/00

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  Y10T29/49222 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05147 ,  H01L2224/05166

摘要： Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.

摘要翻译： 本文公开了用于封装通过这些方法形成的微电子器件和微电子器件的方法。 在一个实施例中，一种方法包括将多个微电子管芯耦合到支撑构件，用介电层覆盖模具和支撑构件的至少一部分，形成通过模具之间的介电层的多个通孔，并且制造 相应通孔中的多个导电连接。 在另一个实施例中，多个微电子器件包括支撑构件，耦合到支撑构件的多个微电子模具，在模具和支撑构件的至少一部分上的电介质层，以及从一个 介电层的第一表面到第二表面。 模具包括集成电路和耦合到集成电路的多个接合焊盘，并且导电连接件设置在管芯之间。