公开(公告)号：US07307266B1

公开(公告)日：2007-12-11

申请号：US10730713

申请日：2003-11-26

申请人： Chen-Kuo Sun ,  Richard C. Eden ,  Ching-Ten Chang ,  Donald J. Albares

发明人： Chen-Kuo Sun ,  Richard C. Eden ,  Ching-Ten Chang ,  Donald J. Albares

IPC分类号： G02B27/00 ,  G02B6/28 ,  G01J1/04 ,  G11C27/02 ,  H03K17/74 ,  H03M1/00

CPC分类号： G11C27/02 ,  G11C27/024 ,  G11C27/026 ,  H03K17/04 ,  H03K17/16 ,  H03K17/74 ,  H03K17/78

摘要： A method and apparatus for optically clocked optoelectronic track and hold (“OCOETH”) device. The OCOETH device includes a diode bridge, input node, at least two current sources and at least two photodetectors. The input node is operatively coupled to the diode bridge and can receive an analog input signal. The at least two current sources are operatively coupled to the diode bridge and can forward bias the diode bridge. The at least two photodetectors are operatively coupled to the diode bridge and can receive an optical input clocking signal, and can reverse bias and forward bias the diode bridge in response to the optical input clocking signal. The hold capacitor is operatively coupled to the diode bridge and can track the analog input signal when the diode bridge is forward biased, and can hold the analog input signal when the diode bridge switches from forward biased to reverse biased.

摘要翻译： 一种用于光时钟光电跟踪和保持（“OCOETH”）设备的方法和装置。 OCOETH装置包括二极管桥，输入节点，至少两个电流源和至少两个光电检测器。 输入节点可操作地耦合到二极管电桥并且可以接收模拟输入信号。 至少两个电流源可操作地耦合到二极管桥并且可以对二极管桥进行正向偏置。 所述至少两个光电检测器可操作地耦合到二极管电桥并且可以接收光输入时钟信号，并且可以响应于光输入时钟信号而反向偏置和向前偏置二极管桥。 保持电容器可操作地耦合到二极管电桥，并且可以在二极管电桥正向偏置时跟踪模拟输入信号，并且当二极管电桥从正向偏置切换到反向偏置时，可以保持模拟输入信号。

公开(公告)号：US5441791A

公开(公告)日：1995-08-15

申请号：US66753

申请日：1993-05-24

申请人： Richard C. Eden

发明人： Richard C. Eden

IPC分类号： B32B15/04 ,  C01B31/06 ,  C30B29/04 ,  F28F3/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/373 ,  H05K1/03 ,  H01L21/58

CPC分类号： H01L21/4803 ,  H01L23/3732 ,  H01L2924/0002 ,  Y10T428/24355 ,  Y10T428/24364 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24529 ,  Y10T428/24975 ,  Y10T428/25 ,  Y10T428/2991 ,  Y10T428/2998 ,  Y10T428/30 ,  Y10T428/31504

摘要： A synthetic diamond wafer grown by deposition from a plasma has a smooth, substrate side face and a rough, deposition side face. The rough face is coated with a bonding agent which fills the valleys and is finished so that its surface is parallel to the substrate side face to permit photolithographic processing of the wafer. Also disclosed is a multi-wafer laminate of two or more diamond film layers bonded together with an interlayer. Smooth, flat outer faces of the layers are oriented mutually parallel. The inner, bonded faces may be rough. A filler of diamond particles in the bonding agent improves the thermal conductivity of the laminate.

摘要翻译： 通过从等离子体沉积而生长的合成金刚石晶片具有光滑的基板侧面和粗糙的沉积侧面。 粗糙的表面涂覆有填充谷的粘合剂并且被完成，使得其表面平行于基底侧面以允许晶片的光刻处理。 还公开了两个或更多个与中间层结合在一起的金刚石膜层的多晶片层压体。 层的平滑，平坦的外表面相互平行取向。 内部粘合面可能很粗糙。 粘合剂中金刚石颗粒的填料提高了层压板的导热性。

公开(公告)号：US5244712A

公开(公告)日：1993-09-14

申请号：US642244

申请日：1991-01-15

申请人： Richard C. Eden

发明人： Richard C. Eden

IPC分类号： B32B15/04 ,  C01B31/06 ,  C30B29/04 ,  F28F3/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/373 ,  H05K1/03

CPC分类号： H01L21/4803 ,  H01L23/3732 ,  H01L2924/0002 ,  Y10T428/24355 ,  Y10T428/24364 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24529 ,  Y10T428/24975 ,  Y10T428/25 ,  Y10T428/2991 ,  Y10T428/2998 ,  Y10T428/30 ,  Y10T428/31504

摘要： A synthetic diamond wafer grown by deposition from a plasma has a smooth, substrate side face and a rough, deposition side face. The rough face is coated with a bonding agent which fills the valleys and is finished so that its surface is parallel to the substrate side face to permit photolithographic processing of the wafer. Also disclosed is a multi-wafer laminate of two or more diamond film layers bonded together with an interlayer. Smooth, flat outer faces of the layers are oriented mutually parallel. The inner, bonded faces may be rough. A filler of diamond particles in the bonding agent improves the thermal conductivity of the laminate.

公开(公告)号：US4110778A

公开(公告)日：1978-08-29

申请号：US808496

申请日：1977-06-21

申请人： Richard C. Eden ,  Kenichi Nakano

发明人： Richard C. Eden ,  Kenichi Nakano

IPC分类号： H01L31/107 ,  H01L27/14

CPC分类号： H01L31/107

摘要： A narrow-band, inverted homo-heterojunction avalanche photodiode, configured in the shape of a mesa situated upon a substrate which is transparent to selected light energy wavelengths. The diode is inverted for operation such that the incoming light energy enters the substrate side, passes through a wavelength selective buffer layer and is absorbed upon entering the succeeding, active region. Avalanche gain is attained by drift from the area of absorption to the high field p-n homo-heterojunction located immediately thereafter. The device exhibits low levels of noise during operation because absorption is occurring in a low field region and because the ionization and breakdown noise associated with lattice mismatches is avoided through the formation of the p-n homo-heterojunction in one continuous growth process. Appropriate passivation of the mesa walls inhibits surface leakage and breakdown effects.

摘要翻译： 窄带，反相同异质结雪崩光电二极管，其被配置为位于对选择的光能波长透明的衬底上的台面形状。 二极管被反相操作，使得入射光能进入衬底侧，通过波长选择缓冲层，并在进入后续有源区时被吸收。 通过从吸收区域漂移到紧邻的高场p-n同异质结获得雪崩增益。 该装置在操作期间表现出低水平的噪声，因为在低场区域中发生吸收，并且由于通过在一个连续生长过程中形成p-n同异质结来避免与晶格失配相关的电离和击穿噪声。 台面壁的适当钝化可以抑制表面渗漏和击穿效应。

公开(公告)号：US4075576A

公开(公告)日：1978-02-21

申请号：US772173

申请日：1977-02-25

申请人： Richard C. Eden

发明人： Richard C. Eden

IPC分类号： H03F3/08 ,  H04B10/158 ,  H03F3/16

CPC分类号： H04B10/693 ,  H03F3/08

摘要： A preamp for coupling to an avalanche photodiode (APD) of an optical receiver has an input stage including a dual gate field effect transistor (FET) and a single gate FET coupled in a cascade arrangement. The dual gate FET has its first gate coupled to the output of the APD, its second gate and source grounded, and its drain driving the gate of the single gate FET in a cascade arrangement. The source of the single gate FET is level-shifted and coupled by means of a feedback resistor to the first gate of the dual gate FET to provide a negative feedback. The output stage is a third FET with its gate coupled through a blocking capacitor to the source of the single gate FET in the input stage and with its drain providing the output of the preamp. In a preferred embodiment, the FETs used are GaAs FETs (GAASFETs).

公开(公告)号：US07019337B2

公开(公告)日：2006-03-28

申请号：US10703921

申请日：2003-11-07

申请人： Richard C. Eden ,  Bruce A. Smetana

发明人： Richard C. Eden ,  Bruce A. Smetana

IPC分类号： H01L29/74

CPC分类号： H01L24/17 ,  H01L23/4824 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/642 ,  H01L27/088 ,  H01L29/41725 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7802 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/33507 ,  H02M3/33576 ,  H02M3/33592 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2224/0401

摘要： Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

摘要翻译： 描述了功率半导体开关器件，功率转换器，集成电路组件，集成电路，功率电流切换方法，形成功率半导体开关器件的方法，功率转换方法，功率半导体开关器件封装方法和形成功率晶体管的方法。 一个示例性方面提供一种功率半导体器件，其包括具有表面的半导体衬底; 以及功率晶体管，其具有平面构造并且包括多个电耦合源和使用所述半导体衬底并且邻近所述表面形成的多个电耦合漏极。

公开(公告)号：US06737301B2

公开(公告)日：2004-05-18

申请号：US09904575

申请日：2001-07-12

申请人： Richard C. Eden ,  Bruce A. Smetana

发明人： Richard C. Eden ,  Bruce A. Smetana

IPC分类号： H01L2182

CPC分类号： H01L24/17 ,  H01L23/4824 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/642 ,  H01L27/088 ,  H01L29/41725 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7802 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/33507 ,  H02M3/33576 ,  H02M3/33592 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2224/0401

摘要： Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

摘要翻译： 描述了功率半导体开关器件，功率转换器，集成电路组件，集成电路，功率电流切换方法，形成功率半导体开关器件的方法，功率转换方法，功率半导体开关器件封装方法和形成功率晶体管的方法。 一个示例性方面提供一种功率半导体器件，其包括具有表面的半导体衬底; 以及功率晶体管，其具有平面构造并且包括多个电耦合源和使用所述半导体衬底并且邻近所述表面形成的多个电耦合漏极。

公开(公告)号：US06553044B1

公开(公告)日：2003-04-22

申请号：US09175235

申请日：1998-10-20

申请人： Richard C. Eden

发明人： Richard C. Eden

IPC分类号： H01S300

CPC分类号： H01S5/4031 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01S5/02216 ,  H01S5/0224 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/0427 ,  H01S5/06226 ,  H01S5/06804 ,  H01S5/4025 ,  H01S5/4087 ,  H01L2924/00014

摘要： Active compensation techniques are used for control of temperature, wavelength, and other characteristics of lasers within a laser array. The laser array includes a plurality of lasers and a plurality of dissipation elements. The dissipation elements can be interstitial to the lasers and can be implemented as non-lasing diodes. The dissipation elements are selectively activated (i.e., turned “on” to dissipate power) to adjust the temperature at the laser junctions. The change in junction temperature allows the lasers to operate at their specified wavelengths. The dissipation elements can be individually controlled and two or more bits of resolution can be provided. Active compensation can be used to adjust (i.e., to compensate) the temperature of selected lasers when one or more lasers are deselected. Active compensation can also be used to adjust (i.e., “tweak”) the wavelengths of the lasers within the laser array to be within their specified wavelengths.

摘要翻译： 有源补偿技术用于控制激光器阵列内的激光器的温度，波长和其他特性。 激光器阵列包括多个激光器和多个耗散元件。 耗散元件可以是激光器的间隙，并且可以被实现为非激光二极管。 选择性地激活耗散元件（即，“开”以耗散功率）来调节激光连接处的温度。 结温变化允许激光器在其指定波长下工作。 可以单独控制耗散元件，并可提供两位或更多位的分辨率。 当取消选择一个或多个激光器时，可以使用有源补偿来调整（即补偿）所选择的激光器的温度。 还可以使用有源补偿来调整（即，“调整”）激光器阵列内的激光波长在其指定波长内。

公开(公告)号：US4405870A

公开(公告)日：1983-09-20

申请号：US214924

申请日：1980-12-10

申请人： Richard C. Eden

发明人： Richard C. Eden

IPC分类号： H03K19/0956 ,  H03K19/094 ,  H03K19/017 ,  H03K19/12 ,  H03K19/20

CPC分类号： H03K19/0956

摘要： Disclosed is a logic circuit with a plurality of AND logic elements, each including a plurality of Schottky diodes with each cathode connected to a logic input and the anodes connected in common to establish an AND output. A diode pull up FET is provided for each AND output, with the source connected to the AND output, the gate connected to the source, and the drain connected to a source of positive bias potential. An OR logic element includes a plurality of Schottky diodes with each anode connected to one of the AND outputs and the cathodes connected in common to establish an OR output, while a diode pull down FET has its drain connected to the OR output, with the gate connected to the source and the source connected to a source of negative bias potential. A level shifting diode is placed between the OR output and the pull down FET. An output FET is connected through its gate to the drain of the diode pull down FET, with the source connected to ground and the drain providing a logic output from the circuit. An output pull up FET has its source connected to the drain of the output FET, the gate connected to the source, and the drain connected to the source of positive bias potential.

摘要翻译： 公开了具有多个AND逻辑元件的逻辑电路，每个逻辑元件包括多个肖特基二极管，每个阴极连接到逻辑输入端，并且共同连接的阳极以建立与输出。 为每个AND输出提供二极管上拉FET，其源极连接到AND输出，栅极连接到源极，漏极连接到正偏置电位源。 OR逻辑元件包括多个肖特基二极管，其中每个阳极连接到一个AND输出，阴极共同连接以建立OR输出，而二极管下拉FET的漏极连接到OR输出，栅极 连接到源极和源极连接到负偏置电位源。 电平移位二极管放置在OR输出和下拉FET之间。 输出FET通过其栅极连接到二极管下拉FET的漏极，源极接地，漏极提供来自电路的逻辑输出。 输出上拉FET的源极连接到输出FET的漏极，栅极连接到源极，漏极连接到正偏置电位源。

公开(公告)号：US06759983B2

公开(公告)日：2004-07-06

申请号：US10107811

申请日：2002-03-28

申请人： Richard C. Eden

发明人： Richard C. Eden

IPC分类号： G01S302

CPC分类号： G01S5/04 ,  G01S3/36 ,  G01S7/021

摘要： The invention relates to methods and devices for precise geolocation of low-power, broadband, amplitude-modulated rf and microwave signals having poor coherency. The invention provides a basis for dramatic improvements in RF receiver technology, offering much higher sensitivity, very strong rejection of unintended signals, and novel direction finding techniques. When mounted on an airborne surveillance platform, the invention can detect and geolocate weak, broadband, incoherent RF and/or microwave signals. Embodiments of the invention are implemented by dual channel receivers (heterodyne or tuned-RF) that use crystal detection and Fast Fourier Transform (FFT) analysis for geolocation. Geolocation is accomplished using a subsystem of phased arrays and an angle of arrival technique.

摘要翻译： 本发明涉及具有差相干性的低功率，宽带，幅度调制rf和微波信号的精确地理定位的方法和装置。 本发明为RF接收机技术的显着改进提供了基础，提供了更高的灵敏度，非常强的拒绝非预期信号以及新颖的方向发现技术。 当安装在机载监视平台上时，本发明可以检测和定位弱，宽带，非相干RF和/或微波信号。 本发明的实施例由对待地理定位使用晶体检测和快速傅立叶变换（FFT）分析的双通道接收器（外差或调谐RF）来实现。 使用相控阵列子系统和到达角技术实现地理定位。