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    MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS
    1.
    发明申请
    MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS 有权
    多芯片封装使用插座等作为基于硅的间插器与穿透硅

    公开(公告)号：US20080295325A1

    公开(公告)日：2008-12-04

    申请号：US11755735

    申请日：2007-05-30

    申请人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    发明人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    IPC分类号： H05K3/36

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L25/0655 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/10253 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

    摘要： The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface of the body, the electrically conductive layer defining a first metal pad layer on the upper surface and a second metal pad layer in contact with the first metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. The method also includes forming a dielectric layer between the adjacent metal pads in the first and second pad layers. The method also includes coupling a plurality of elements to the second metal pad layer. After the coupling the elements, the method includes thinning the body through a lower surface and exposing the electrically insulating layer in the vias. The method also includes removing a portion of the electrically insulating layer in the vias, and coupling the electrically conductive layer to a substrate, wherein the body is positioned between the elements and the substrate. Other embodiments are described and claimed.

    摘要翻译： 描述了包括具有插入件的组件的电子组件的形成。 在一个实施例中，一种方法包括形成多个部分延伸通过主体的通孔，通孔包括由主体限定的侧壁。 绝缘层形成在主体的侧壁和上表面上。 导电层形成在通孔的绝缘层上和主体的上表面上，导电层在上表面上限定第一金属焊盘层和与第一金属焊盘层接触的第二金属焊盘层 ，所述第二金属焊盘层在相邻焊盘之间具有比所述第一金属焊盘层更密的间距。 该方法还包括在第一和第二焊盘层中的相邻金属焊盘之间形成电介质层。 该方法还包括将多个元件耦合到第二金属焊盘层。 在耦合这些元件之后，该方法包括通过下表面使本体变薄并暴露通孔中的电绝缘层。 该方法还包括去除通孔中电绝缘层的一部分，以及将导电层耦合到衬底，其中本体位于元件和衬底之间。 描述和要求保护其他实施例。

    Methods for making multi-chip packaging using an interposer
    2.
    发明授权
    Methods for making multi-chip packaging using an interposer 有权
    使用插入片进行多芯片封装的方法

    公开(公告)号：US08387240B2

    公开(公告)日：2013-03-05

    申请号：US12955816

    申请日：2010-11-29

    申请人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    发明人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    IPC分类号： H01K3/10

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L25/0655 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/10253 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

    摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.

    摘要翻译： 在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。 电绝缘层形成在主体的侧壁和上表面上。 在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的 间距比第一金属垫。 在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。 身体通过下表面变薄，并且通孔中的电绝缘层被暴露。 在变薄之后，去除通孔中的电绝缘层的一部分。 主体耦合到基板。

    Multi-chip packaging using an interposer with through-vias
    6.
    发明授权
    Multi-chip packaging using an interposer with through-vias 有权
    多芯片封装采用插入式通孔

    公开(公告)号：US07841080B2

    公开(公告)日：2010-11-30

    申请号：US11755735

    申请日：2007-05-30

    申请人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    发明人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    IPC分类号： H01K3/22

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L25/0655 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/10253 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

    摘要： One embodiment relates to forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. A plurality of electronic elements are coupled to the second metal pads. After the coupling the elements, the body is thinned through a lower surface. A portion of the insulating layer in the vias is removed and the electrically conductive layer is coupled to a substrate.

    摘要翻译： 一个实施例涉及形成多个部分地穿过主体的通孔，通孔包括由主体限定的侧壁。 绝缘层形成在主体的侧壁和上表面上。 在绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有比第一金属焊盘更致密的间距。 在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。 多个电子元件耦合到第二金属焊盘。 在连接元件之后，主体通过下表面变薄。 去除通孔中的绝缘层的一部分，并且将导电层耦合到衬底。