公开(公告)号：US20090308527A1

公开(公告)日：2009-12-17

申请号：US12137553

申请日：2008-06-12

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Bo-Yu Tseng

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Bo-Yu Tseng

IPC分类号： B32B38/10

CPC分类号： H05K3/427 ,  B32B37/025 ,  B32B38/10 ,  B32B2038/0016 ,  B32B2305/076 ,  B32B2311/00 ,  B32B2457/08 ,  C22C1/002 ,  H05K3/025 ,  H05K3/108 ,  H05K3/382 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384

摘要： A method for fabricating a circuit trace on a core board having a buried hole is provided. The method includes: providing a carrier plate having a detachable metal layer, an etching barrier layer, and a metal layer sequentially stacked thereon; roughening the metal layer which can be completely roughened; laminating the bonded metal layer, the etching barrier layer, the detachable metal layer and the carrier plate onto a dielectric, wherein the metal layer faces and contacts with the dielectric; and then removing the carrier plate therefrom. As such, even if the dielectric is difficult to be completely roughened, the roughened metal layer can enhance the bondability between the metal layer and the dielectric. The metal layer is processed to become the circuit trace later.

摘要翻译： 提供了一种用于在具有掩埋孔的芯板上制造电路迹线的方法。 该方法包括：提供具有可分离的金属层，蚀刻阻挡层和顺序堆叠在其上的金属层的载体板; 使可以完全粗糙化的金属层变粗糙; 将接合的金属层，蚀刻阻挡层，可拆卸金属层和载体板层压到电介质上，其中金属层面对并与电介质接触; 然后从其移除载体板。 因此，即使电介质难以完全粗糙化，粗糙化的金属层也可以提高金属层与电介质的结合性。 金属层后处理成电路迹线。

公开(公告)号：US20100170088A1

公开(公告)日：2010-07-08

申请号：US12725460

申请日：2010-03-17

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC分类号： H05K3/10

CPC分类号： H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

摘要： Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

摘要翻译： 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。

公开(公告)号：US20120228011A1

公开(公告)日：2012-09-13

申请号：US13043462

申请日：2011-03-09

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC分类号： H05K1/09 ,  H05K1/00

CPC分类号： H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2224/05552

摘要： Disclosed is a semiconductor load board, including a substrate, a plurality of connection pads, a patterned circuit layer, a dielectric layer, a plurality of solder pads, and a plurality of solders. The connection pads and the patterned circuit layer are located on the substrate. The dielectric layer is formed on the substrate, the connection pads and the patterned circuit layer, and has a plurality of openings corresponding to the plurality of connection pads. The solder pads are formed in the openings, and the width of the solder pads is smaller than or equals to the maximum width of the openings of the dielectric layer, and a protruding portion which has a width smaller than the minimum width of the openings of the dielectric layer can also be formed, such that the problems of short-circuit failure and electrical interference can be reduced.

摘要翻译： 公开了一种半导体负载板，包括基板，多个连接焊盘，图案化电路层，电介质层，多个焊盘和多个焊料。 连接焊盘和图案化电路层位于衬底上。 介电层形成在基板上，连接焊盘和图案化电路层上，并且具有对应于多个连接焊盘的多个开口。 焊盘形成在开口中，并且焊盘的宽度小于或等于电介质层的开口的最大宽度，并且宽度小于开口的最小宽度的突出部分 还可以形成电介质层，从而可以减少短路故障和电气干扰的问题。

公开(公告)号：US08083954B2

公开(公告)日：2011-12-27

申请号：US12131932

申请日：2008-06-03

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC分类号： H01B13/00

CPC分类号： B32B37/226 ,  B32B38/06 ,  B32B2305/342 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83132 ,  H05K1/023 ,  H05K1/185 ,  H05K1/188 ,  H05K3/025 ,  H05K2201/0355 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

摘要： A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.

摘要翻译： 一种用于制造部件嵌入式PCB的方法包括：提供其上镀有电镀金属层的载体板; 将电子部件设置在载体板的电镀金属层上; 通过电介质膜将金属层层叠在其上设置有电子部件的电镀金属层和载体板上; 移除载体板并暴露电镀金属层; 并且将金属层和电镀金属层中的至少一个图案化为电路层。

公开(公告)号：US07875809B2

公开(公告)日：2011-01-25

申请号：US11766194

申请日：2007-06-21

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC分类号： H05K1/00

CPC分类号： H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

摘要： A circuit board includes a core layer substrate having a plated through hole filled with a dielectric material. The plated through hole has a sidewall coated with an inner electroless copper layer, and an electroplated metal layer plated on the inner electroless copper layer before the plated through hole is filled with the dielectric material. The outer portion of the filled plated through hole is thicker than the center portion and tapered toward the center portion to form a depressed surface on the filled plated through hole. The core layer substrate is covered with a patterned electroless copper layer and a patterned electroplated copper layer that connect with the inner electroless copper layer and electroplated metal layer of the plated through hole. The patterned electroplated copper layer forms a flat copper pad above the plated through hole.

摘要翻译： 电路板包括具有填充有介电材料的电镀通孔的芯层基板。 电镀通孔具有涂覆有内部化学镀铜层的侧壁和在电镀通孔填充有电介质材料之前镀在内部化学镀铜层上的电镀金属层。 填充电镀通孔的外部比中心部分厚，并且朝向中心部分逐渐变细，以在填充的电镀通孔上形成凹陷表面。 芯层衬底被覆有图案化的无电铜层和与电镀通孔的内部化学镀铜层和电镀金属层连接的图案化电镀铜层。 图案化的电镀铜层在电镀通孔上方形成平坦的铜焊盘。

公开(公告)号：US20100307666A1

公开(公告)日：2010-12-09

申请号：US12479811

申请日：2009-06-07

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC分类号： B32B37/00

CPC分类号： B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

摘要： A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

摘要翻译： 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

公开(公告)号：US20100075497A1

公开(公告)日：2010-03-25

申请号：US12236493

申请日：2008-09-23

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC分类号： H01L21/44 ,  H01L21/288

CPC分类号： H05K3/242 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2203/1476 ,  H05K2203/1581

摘要： A non-plating line (NPL) plating method is provided. The NPL plating method is featured in that at first it forms a circuit layer on a bump side only, and therefore a plating current can be transmitted via a plating metal layer on a ball side to the circuit layer (enclosed by an insulation layer, e.g., a solder resist or a photoresist) on the bump side, and thus forming a protection layer, e.g., plating gold, on the plating metal layer on the circuit layer and the ball side. In such a way, the plating gold is formed after the insulation layer, so that there won't be any plating gold existed beneath the insulation layer of the bump side (connected with dies). Hence, the insulation layer can be prevented from dropping off from the protection layer, i.e., the plating gold, and thus the reliability of the products can be improved.

摘要翻译： 提供非电镀线（NPL）电镀方法。 NPL镀覆方法的特征在于，它首先仅在凸块侧形成电路层，因此电镀电流可以通过球侧的电镀金属层传输到电路层（由绝缘层包围，例如 ，阻焊剂或光致抗蚀剂），从而在电路层和球侧的电镀金属层上形成保护层，例如镀金。 以这种方式，在绝缘层之后形成电镀金，使得在凸起侧（与模具连接）的绝缘层下方不存在镀金。 因此，可以防止绝缘层从保护层即电镀金脱落，从而可以提高产品的可靠性。

公开(公告)号：US20090111213A1

公开(公告)日：2009-04-30

申请号：US12347964

申请日：2008-12-31

申请人： Chien-Wei Chang ,  Ting-Hao Lin

发明人： Chien-Wei Chang ,  Ting-Hao Lin

IPC分类号： H01L21/50

CPC分类号： H01L21/4846 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/205 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density.

摘要翻译： 高密度细线结构主要包括：具有相似结构的两个板和用于梳理两个板的电介质膜。 两块板之间的半导体器件相互相对，两块板组合起来。 两个板各自包括细线电路，同一表面上的绝缘层，以及安装在细线电路上方的半导体器件。 未被焊接掩模覆盖的电路的表面被制成焊盘。 衬垫填充有用于与另一半导体器件电连接的锡球。 使用电镀而不是蚀刻方法来形成细线电路层，并且去除在制造过程期间或结束时需要的载体和金属阻挡层，以增加用于实现该目的的物体的布线密度 高密度。

公开(公告)号：US08377815B2

公开(公告)日：2013-02-19

申请号：US13043463

申请日：2011-03-09

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pad is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

摘要翻译： 公开了一种半导体负载板的制造方法。 该制造方法包括第一导电层形成步骤，第一图案化步骤，介电层形成步骤，钻孔步骤，第二导电层形成步骤，第二图案化步骤或两次图案化步骤，以及焊料连接步骤 。 在第二图案化步骤或二次图案化步骤中，在电介质层的开口中形成焊料焊盘，其中每个焊盘的高度高于电介质的高度，并且每个焊盘的宽度相等 达到或小于开口的最大宽度，使得在相同的区域中设置更宽的间隔，并且可以减少短路故障和电气干扰的问题。

公开(公告)号：US08312624B1

公开(公告)日：2012-11-20

申请号：US13304340

申请日：2011-11-24

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

IPC分类号： H05K3/02

CPC分类号： H05K3/427 ,  H05K1/0206 ,  H05K3/421 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method for manufacturing a heat dissipation structure of a printed circuit board includes: forming a barrier layer on the dimple in the first copper plating layer; forming a nickel plating layer; removing the nickel plating layer and the barrier layer on the dimple; forming a second copper plating layer to make the total height of the first copper plating layer and the second copper plating layer in the second opening higher than that of the first copper plating layer in the first opening; filling the dimple in the second copper plating layer with an etching-resistant material; removing the second copper plating layer; removing the nickel plating layer and the etching-resistant material to make the second copper plating layer in the second opening being at the same height as the first copper plating layer in the first opening; and forming the heat dissipation structure by photolithography.

摘要翻译： 制造印刷电路板的散热结构的方法包括：在第一镀铜层的凹坑上形成阻挡层; 形成镀镍层; 去除凹坑上的镀镍层和阻挡层; 形成第二镀铜层，使第二开口中的第一镀铜层和第二镀铜层的总高度高于第一开口中的第一镀铜层的总高度; 用耐腐蚀材料填充第二镀铜层中的凹坑; 去除所述第二镀铜层; 去除镀镍层和耐腐蚀材料，使得第二开口中的第二镀铜层处于与第一开口中的第一铜镀层相同的高度; 并通过光刻法形成散热结构。