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公开(公告)号：US08952513B2
公开(公告)日：2015-02-10
申请号：US13279545
申请日：2011-10-24
申请人： Choong-bin Yim , Dae-Young Choi , Mi-Yeon Kim , Ji-yong Park
发明人： Choong-bin Yim , Dae-Young Choi , Mi-Yeon Kim , Ji-yong Park
IPC分类号： H01L23/48 , H01L23/52 , H01L23/28 , H01L23/498 , H01L23/00 , H01L25/10 , H01L23/31 , H01L23/538
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/481 , H01L23/49833 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/0558 , H01L2224/056 , H01L2224/13025 , H01L2224/16225 , H01L2224/16227 , H01L2224/2402 , H01L2224/24051 , H01L2224/24105 , H01L2224/24226 , H01L2224/245 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73259 , H01L2224/73265 , H01L2224/82 , H01L2224/82105 , H01L2225/0651 , H01L2225/06565 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/1815 , H01L2924/18161 , H01L2924/00 , H01L2924/00012 , H01L2924/15322 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.
摘要翻译： 堆叠型半导体封装以及叠层型半导体封装的制造方法。 叠层型半导体封装包括：下半导体封装，包括电路板，设置在电路板的上表面上的半导体芯片，排列在电路板的上表面周围的半导体芯片的通孔焊盘， 以及封装层，其封装电路板的上表面并具有通孔，通孔穿过该通孔; 并且层叠在封装层上的上半导体封装电连接到下半导体封装，并且包括形成在上半导体封装的下表面上的内部连接端子。
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公开(公告)号：US08759959B2
公开(公告)日：2014-06-24
申请号：US13029736
申请日：2011-02-17
申请人： Choong-Bin Yim , Seung-Kon Mok , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim
发明人： Choong-Bin Yim , Seung-Kon Mok , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim
CPC分类号： H01L25/50 , H01L24/73 , H01L25/105 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/01029 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2924/00012
摘要： Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.
摘要翻译： 半导体封装包括第一半导体封装，包括第一印刷电路板和安装在第一印刷电路板上的第一半导体器件，以及堆叠在第一半导体封装上的第二半导体封装，并且包括第二印刷电路板和第二半导体 装置安装在第二印刷电路板上。 半导体封装包括至少一个第一通孔，其通过第一半导体器件将第二半导体封装电连接到第一印刷电路板。
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公开(公告)号：US20110215451A1
公开(公告)日：2011-09-08
申请号：US13029736
申请日：2011-02-17
申请人： Choong-Bin Yim , Seung-Kon Mok , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim
发明人： Choong-Bin Yim , Seung-Kon Mok , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim
IPC分类号： H01L25/11
CPC分类号： H01L25/50 , H01L24/73 , H01L25/105 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/01029 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2924/00012
摘要： Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.
摘要翻译： 半导体封装包括第一半导体封装，包括第一印刷电路板和安装在第一印刷电路板上的第一半导体器件，以及堆叠在第一半导体封装上的第二半导体封装，并且包括第二印刷电路板和第二半导体 装置安装在第二印刷电路板上。 半导体封装包括至少一个第一通孔，其通过第一半导体器件将第二半导体封装电连接到第一印刷电路板。
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公开(公告)号：US08754515B2
公开(公告)日：2014-06-17
申请号：US13614931
申请日：2012-09-13
申请人： Tae-Hun Kim , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
发明人： Tae-Hun Kim , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
IPC分类号： H01L23/02 , H01L21/00 , H01L25/065 , H01L25/10 , H01L25/00 , H01L21/78 , H01L23/48 , H01L23/00 , H01L23/31
CPC分类号： H01L23/5226 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L24/14 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/13022 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/94 , H01L2225/06541 , H01L2225/06565 , H01L2225/1005 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/01019 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2224/11 , H01L2924/00012
摘要： Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
摘要翻译： 提供了一种形成封装封装的方法。 使用晶片级成型工艺形成覆盖晶片的封装。 晶片包括多个半导体芯片和穿过半导体芯片的多个通孔硅通孔（TSV）。 密封剂可以具有与TSV对齐的开口。 密封剂和半导体芯片被分割以形成多个半导体封装。 另一个半导体封装堆叠在从半导体封装中选择的一个上。 另一个半导体封装电连接到TSV。
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5.发明授权Printed circuit board having different sub-core layers and semicondutor package comprising the same 有权具有不同子芯层的印刷电路板和包括其的半导体封装公开(公告)号：US08525341B2
公开(公告)日：2013-09-03
申请号：US13240083
申请日：2011-09-22
申请人： Hyun-Ki Kim , Dae-Young Choi , Mi-Yeon Kim
发明人： Hyun-Ki Kim , Dae-Young Choi , Mi-Yeon Kim
CPC分类号： H05K3/4602 , H01L23/49822 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/15311 , H05K3/4608 , H05K2201/068 , H05K2201/09136 , H01L2924/00
摘要： Provided are a printed circuit board (PCB) and a semiconductor package including the same. The PCB includes a core layer having a stacked structure including at least a first layer made of a first material that has a first coefficient of thermal expansion (CTE) and a second layer made of a second material that has a second CTE different from the first CTE, an upper wiring layer disposed on a first surface of the core layer, and a lower wiring layer disposed on a second surface of the core layer opposite the first surface.
摘要翻译： 提供了一种印刷电路板（PCB）和包括其的半导体封装。 PCB包括具有层叠结构的芯层，该堆叠结构至少包括由具有第一热膨胀系数（CTE）的第一材料制成的第一层和由具有第二CTE的第二材料制成的第二层，第二层具有不同于第一 CTE，设置在芯层的第一表面上的上布线层和布置在与第一表面相对的芯层的第二表面上的下布线层。
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公开(公告)号：US20110291294A1
公开(公告)日：2011-12-01
申请号：US13049377
申请日：2011-03-16
申请人： Sang-Uk Kim , Jin-woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
发明人： Sang-Uk Kim , Jin-woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/147 , H01L23/13 , H01L23/49827 , H01L23/5385 , H01L24/45 , H01L24/48 , H01L25/105 , H01L25/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/48225 , H01L2224/48227 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/00014 , H01L2924/00012
摘要： A multi-chip package may include a first semiconductor package, a second semiconductor package and an interposer chip. The second semiconductor package may be arranged over the first semiconductor package. The interposer chip may be interposed between the first semiconductor package and the second semiconductor package. The interposer chip may have a receiving groove configured to receive the first semiconductor package. Thus, electrical connection reliability between the first semiconductor package and the second semiconductor package may be improved under a condition that the connecting terminals may have small sizes.
摘要翻译： 多芯片封装可以包括第一半导体封装，第二半导体封装和插入器芯片。 第二半导体封装可以布置在第一半导体封装之上。 插入器芯片可以插入在第一半导体封装和第二半导体封装之间。 插入器芯片可以具有被配置为接收第一半导体封装的接收槽。 因此，在连接端子可以具有小尺寸的条件下，可以提高第一半导体封装和第二半导体封装之间的电连接可靠性。
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公开(公告)号：US20110237027A1
公开(公告)日：2011-09-29
申请号：US13027511
申请日：2011-02-15
申请人： Tae-Hun Kim , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
发明人： Tae-Hun Kim , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
IPC分类号： H01L21/50
CPC分类号： H01L23/5226 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L24/14 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/13022 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/94 , H01L2225/06541 , H01L2225/06565 , H01L2225/1005 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/01019 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2224/11 , H01L2924/00012
摘要： Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
摘要翻译： 提供了一种形成封装封装的方法。 使用晶片级成型工艺形成覆盖晶片的封装。 晶片包括多个半导体芯片和穿过半导体芯片的多个通孔硅通孔（TSV）。 密封剂可以具有与TSV对齐的开口。 密封剂和半导体芯片被分割以形成多个半导体封装。 另一个半导体封装堆叠在从半导体封装中选择的一个上。 另一个半导体封装电连接到TSV。
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公开(公告)号：US08531034B2
公开(公告)日：2013-09-10
申请号：US13244506
申请日：2011-09-25
申请人： Hak-Kyoon Byun , Dae-Young Choi , Mi-Yeon Kim
发明人： Hak-Kyoon Byun , Dae-Young Choi , Mi-Yeon Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/17179 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00013 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.
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公开(公告)号：US20130001800A1
公开(公告)日：2013-01-03
申请号：US13614931
申请日：2012-09-13
申请人： Tae-Hun KIM , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
发明人： Tae-Hun KIM , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L24/14 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/13022 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/94 , H01L2225/06541 , H01L2225/06565 , H01L2225/1005 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/01019 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2224/11 , H01L2924/00012
摘要： Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
摘要翻译： 提供了一种形成封装封装的方法。 使用晶片级成型工艺形成覆盖晶片的封装。 晶片包括多个半导体芯片和穿过半导体芯片的多个通孔硅通孔（TSV）。 密封剂可以具有与TSV对齐的开口。 密封剂和半导体芯片被分割以形成多个半导体封装。 另一个半导体封装堆叠在从半导体封装中选择的一个上。 另一个半导体封装电连接到TSV。
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公开(公告)号：US08293580B2
公开(公告)日：2012-10-23
申请号：US13027511
申请日：2011-02-15
申请人： Tae-Hun Kim , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
发明人： Tae-Hun Kim , Jin-Woo Park , Dae-Young Choi , Mi-Yeon Kim , Sun-Hye Lee
CPC分类号： H01L23/5226 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L24/14 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/13022 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/94 , H01L2225/06541 , H01L2225/06565 , H01L2225/1005 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/01019 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2224/11 , H01L2924/00012
摘要： Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
摘要翻译： 提供了一种形成封装封装的方法。 使用晶片级成型工艺形成覆盖晶片的封装。 晶片包括多个半导体芯片和穿过半导体芯片的多个通孔硅通孔（TSV）。 密封剂可以具有与TSV对齐的开口。 密封剂和半导体芯片被分割以形成多个半导体封装。 另一个半导体封装堆叠在从半导体封装中选择的一个上。 另一个半导体封装电连接到TSV。
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