公开(公告)号：US20100078791A1

公开(公告)日：2010-04-01

申请号：US12547662

申请日：2009-08-26

申请人： Choong-bin Yim ,  Tae-je Cho

发明人： Choong-bin Yim ,  Tae-je Cho

IPC分类号： H01L25/11 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049

摘要： A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.

摘要翻译： 半导体封装包括：衬底，其包括设置在其第一表面上的芯片安装单元和设置在芯片安装单元的外部区域上的焊盘形成单元。 半导体封装还包括设置在基板的焊盘形成单元上的多个焊盘，设置在基板的芯片安装单元上的半导体芯片，设置在半导体芯片和焊盘形成之间的基板的第一表面上的坝 单元，并且其中所述坝将所述焊盘的至少一部分与所述半导体芯片分离。 此外，半导体封装还包括设置在半导体芯片的有源表面和基板的第一表面之间的底部填充材料，并且由于表面张力，坝的上表面被倒圆。

公开(公告)号：US20110275177A1

公开(公告)日：2011-11-10

申请号：US13182588

申请日：2011-07-14

申请人： Choong-bin Yim ,  Tae-je Cho

发明人： Choong-bin Yim ,  Tae-je Cho

IPC分类号： H01L21/58

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049

摘要： A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.

摘要翻译： 半导体封装包括：衬底，其包括设置在其第一表面上的芯片安装单元和设置在芯片安装单元的外部区域上的焊盘形成单元。 半导体封装还包括设置在基板的焊盘形成单元上的多个焊盘，设置在基板的芯片安装单元上的半导体芯片，设置在半导体芯片和焊盘形成之间的基板的第一表面上的坝 单元，并且其中所述坝将所述焊盘的至少一部分与所述半导体芯片分离。 此外，半导体封装还包括设置在半导体芯片的有源表面和基板的第一表面之间的底部填充材料，并且由于表面张力，坝的上表面被倒圆。

公开(公告)号：US08187921B2

公开(公告)日：2012-05-29

申请号：US13182588

申请日：2011-07-14

申请人： Choong-bin Yim ,  Tae-je Cho

发明人： Choong-bin Yim ,  Tae-je Cho

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049

摘要： A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.

摘要翻译： 半导体封装包括：衬底，其包括设置在其第一表面上的芯片安装单元和设置在芯片安装单元的外部区域上的焊盘形成单元。 半导体封装还包括设置在基板的焊盘形成单元上的多个焊盘，设置在基板的芯片安装单元上的半导体芯片，设置在半导体芯片和焊盘形成之间的基板的第一表面上的坝 单元，并且其中所述坝将所述焊盘的至少一部分与所述半导体芯片分离。 此外，半导体封装还包括设置在半导体芯片的有源表面和基板的第一表面之间的底部填充材料，并且由于表面张力，坝的上表面被倒圆。

公开(公告)号：US07999368B2

公开(公告)日：2011-08-16

申请号：US12547662

申请日：2009-08-26

申请人： Choong-bin Yim ,  Tae-je Cho

发明人： Choong-bin Yim ,  Tae-je Cho

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049

摘要： A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.

摘要翻译： 半导体封装包括：衬底，其包括设置在其第一表面上的芯片安装单元和设置在芯片安装单元的外部区域上的焊盘形成单元。 半导体封装还包括设置在基板的焊盘形成单元上的多个焊盘，设置在基板的芯片安装单元上的半导体芯片，设置在半导体芯片和焊盘形成之间的基板的第一表面上的坝 单元，并且其中所述坝将所述焊盘的至少一部分与所述半导体芯片分离。 此外，半导体封装还包括设置在半导体芯片的有源表面和基板的第一表面之间的底部填充材料，并且由于表面张力，坝的上表面被倒圆。

公开(公告)号：US08803334B2

公开(公告)日：2014-08-12

申请号：US13672898

申请日：2012-11-09

申请人： Yun-seok Choi ,  Tae-je Cho

发明人： Yun-seok Choi ,  Tae-je Cho

IPC分类号： H01L25/07 ,  H01L25/00 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/31

CPC分类号： H01L25/074 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552

摘要： A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.

摘要翻译： 一种半导体封装，包括基板，设置在所述基板上的芯片堆叠部分，并且包括多个第一半导体芯片，设置在所述芯片堆叠部分上的至少一个第二半导体芯片，以及信号传输介质，用于将所述至少一个第二半导体芯片 半导体芯片和基板，使得芯片堆叠部分是平行六面体结构，其包括作为多个第一半导体芯片的半导体芯片的第一芯片，并且包括硅通孔（TSV），第二芯片是 多个第一半导体芯片中的另一个半导体芯片，并通过TSV电连接到第一芯片;以及内部密封构件，用于填充第一芯片和第二芯片之间的空间。

公开(公告)号：US20150130030A1

公开(公告)日：2015-05-14

申请号：US14541121

申请日：2014-11-13

申请人： Keum-hee Ma ,  Tae-je Cho ,  Ji-hwang Kim

发明人： Keum-hee Ma ,  Tae-je Cho ,  Ji-hwang Kim

IPC分类号： H01L25/10 ,  H01L23/48 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor package includes: a package base substrate; at least one first semiconductor chip disposed on the package base substrate; a first molding member disposed at a same level as the at least one first semiconductor chip and that does not cover an upper surface of the at least one first semiconductor chip; at least one second semiconductor chip stacked on the at least one first semiconductor chip so as to extend over the at least one first semiconductor chip and the first molding member, wherein the at least one first semiconductor chip and at least part of the first molding member are disposed between the package base substrate and the at least one second semiconductor chip; and a second molding member disposed at a same level as the at least one second semiconductor chip.

摘要翻译： 半导体封装包括：封装基底; 设置在所述封装基板上的至少一个第一半导体芯片; 第一模制构件，其设置在与所述至少一个第一半导体芯片相同的水平面处，并且不覆盖所述至少一个第一半导体芯片的上表面; 至少一个第二半导体芯片，堆叠在所述至少一个第一半导体芯片上，以便在所述至少一个第一半导体芯片和所述第一模制构件上延伸，其中所述至少一个第一半导体芯片和所述第一模制构件的至少一部分 设置在所述封装基底基板和所述至少一个第二半导体芯片之间; 以及设置在与所述至少一个第二半导体芯片相同水平面的第二模制构件。

公开(公告)号：US20130175706A1

公开(公告)日：2013-07-11

申请号：US13672898

申请日：2012-11-09

申请人： Yun-seok Choi ,  Tae-je Cho

发明人： Yun-seok Choi ,  Tae-je Cho

IPC分类号： H01L25/07

CPC分类号： H01L25/074 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552

摘要： A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.

摘要翻译： 一种半导体封装，包括基板，设置在所述基板上的芯片堆叠部分，并且包括多个第一半导体芯片，设置在所述芯片堆叠部分上的至少一个第二半导体芯片，以及信号传输介质，用于将所述至少一个第二半导体芯片 半导体芯片和基板，使得芯片堆叠部分是平行六面体结构，其包括作为多个第一半导体芯片的半导体芯片的第一芯片，并且包括硅通孔（TSV），第二芯片是 多个第一半导体芯片中的另一个半导体芯片，并通过TSV电连接到第一芯片;以及内部密封构件，用于填充第一芯片和第二芯片之间的空间。

公开(公告)号：US20130001797A1

公开(公告)日：2013-01-03

申请号：US13531289

申请日：2012-06-22

申请人： Yun-seok Choi ,  Hee-seok Lee ,  Tae-je Cho

发明人： Yun-seok Choi ,  Hee-seok Lee ,  Tae-je Cho

IPC分类号： H01L23/498

CPC分类号： H01L25/105 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331

摘要： A package on package (PoP) employing a through substrate via (TSV) technique in order to reduce the size of a semiconductor chip, has vertically narrow pitches, and forms a higher number of connection terminals. The PoP include a first substrate with a recess disposed in a first surface of the substrate, and a semiconductor chip disposed at the recess. The PoP also includes a semiconductor package connected to the first semiconductor package. The first substrate includes TSVs for electronically connecting the semiconductor package and the semiconductor chip, and routing lines for re-distributing the signals/and or power transmitted via the TSVs.

摘要翻译： 为了减小半导体芯片的尺寸，采用直通衬底通孔（TSV）技术的封装（PoP）具有垂直窄的间距，并且形成更多数量的连接端子。 PoP包括具有设置在基板的第一表面中的凹部的第一基板和设置在凹部处的半导体芯片。 PoP还包括连接到第一半导体封装的半导体封装。 第一衬底包括用于电连接半导体封装和半导体芯片的TSV以及用于重新分配通过TSV传输的信号和/或功率的路由线。

公开(公告)号：US09929022B2

公开(公告)日：2018-03-27

申请号：US15231880

申请日：2016-08-09

申请人： Seok-hyun Lee ,  Yun-seok Choi ,  Tae-je Cho ,  Jin-woo Park

发明人： Seok-hyun Lee ,  Yun-seok Choi ,  Tae-je Cho ,  Jin-woo Park

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L21/31144 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1815 ,  H01L2224/83

摘要： A method of manufacturing a semiconductor package includes: providing a package substrate having a first surface and a second surface opposite the first surface; providing a first semiconductor chip on the package substrate, the first semiconductor chip having a first surface facing the second surface of the package substrate, a second surface opposite the first surface of the first semiconductor chip, and lateral surfaces extending from the first surface of the first semiconductor chip to the second surface of the first semiconductor chip; providing a molding layer covering the lateral surfaces of the first semiconductor chip and covering the second surface of the package substrate; and providing a plurality of through-molding conductive vias outside the lateral surfaces of the first semiconductor chip. The through-molding conductive vias may be formed before forming the molding layer and may pass through the molding layer. The through-molding conductive vias may extend beyond a first surface of the molding layer.

公开(公告)号：US20170069532A1

公开(公告)日：2017-03-09

申请号：US15231880

申请日：2016-08-09

申请人： Seok-hyun Lee ,  Yun-seok Choi ,  Tae-je Cho ,  Jin-woo Park

发明人： Seok-hyun Lee ,  Yun-seok Choi ,  Tae-je Cho ,  Jin-woo Park

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L21/31144 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1815 ,  H01L2224/83

摘要： A method of manufacturing a semiconductor package includes: providing a package substrate having a first surface and a second surface opposite the first surface; providing a first semiconductor chip on the package substrate, the first semiconductor chip having a first surface facing the second surface of the package substrate, a second surface opposite the first surface of the first semiconductor chip, and lateral surfaces extending from the first surface of the first semiconductor chip to the second surface of the first semiconductor chip; providing a molding layer covering the lateral surfaces of the first semiconductor chip and covering the second surface of the package substrate; and providing a plurality of through-molding conductive vias outside the lateral surfaces of the first semiconductor chip. The through-molding conductive vias may be formed before forming the molding layer and may pass through the molding layer. The through-molding conductive vias may extend beyond a first surface of the molding layer.

摘要翻译： 制造半导体封装的方法包括：提供具有第一表面和与第一表面相对的第二表面的封装衬底; 在所述封装衬底上提供第一半导体芯片，所述第一半导体芯片具有面向所述封装衬底的第二表面的第一表面，与所述第一半导体芯片的第一表面相对的第二表面，以及从所述第一半导体芯片的第一表面延伸的侧表面 第一半导体芯片到第一半导体芯片的第二表面; 提供覆盖所述第一半导体芯片的侧表面并覆盖所述封装衬底的所述第二表面的成型层; 以及在所述第一半导体芯片的侧表面之外提供多个贯穿模制导电通孔。 可以在形成模制层之前形成贯穿模制导电通孔并且可以穿过模制层。 贯穿模制导电通孔可以延伸超过模制层的第一表面。