公开(公告)号：US06593662B1

公开(公告)日：2003-07-15

申请号：US09631343

申请日：2000-08-02

申请人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

发明人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

IPC分类号： H01L2348

CPC分类号： H01L24/33 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by one on the upper surface of the carrier, and a number of bonding pads are located around each die. The spacers are located between two adjacent dies. Adhesive layers located between the spacers, the dies, and the carrier for adhering layers therebetween. The conducting lines are respectively electrically connected between each of the bonding pads of the dies and the carrier. And the mold compound is formed over the upper surface of the carrier, for encapsulating the spacers, the dies and the adhesive layers. A substrate with solder balls or a lead frame having pins is suitable for serving as the carrier.

摘要翻译： 堆叠管芯封装结构包括载体，管芯，间隔物，粘合剂层，导电线，模具化合物和焊球。 载体具有与上表面相对的上表面和后表面。 基本上具有相同尺寸的模具在载体的上表面上一个接一个堆叠，并且多个焊盘位于每个管芯周围。 间隔件位于两个相邻的模具之间。 位于间隔件，模具和载体之间的粘合层，用于在其间粘合层。 导体线分别电连接在管芯和载体的每个接合焊盘之间。 并且模制化合物形成在载体的上表面上，用于封装间隔物，模具和粘合剂层。 具有焊球或具有引脚的引线框架的基板适合用作载体。

公开(公告)号：US06528722B2

公开(公告)日：2003-03-04

申请号：US09235095

申请日：1999-01-21

申请人： Chien Ping Huang ,  Randy H. Y. Lo

发明人： Chien Ping Huang ,  Randy H. Y. Lo

IPC分类号： H01L2328

CPC分类号： H05K13/0465 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A Ball Grid Array (BGA) semiconductor package with exposed base layer includes a base layer having an opening portion in the center thereof and formed with a plurality of holes about the opening portion. A plurality of leads are attached to a second surface of the base layer and each of the leads is connected to a corresponding hole in the base layer. A semiconductor chip is attached and electrically connected to the leads. The semiconductor chip and the leads are covered by an encapsulant formed by an encapsulating compound, leaving a first surface of the base layer exposed. A plurality of solder balls are planted in the holes in the base layer, which are electrically bonded to the leads so as to electrically connect the semiconductor chip to external devices. In this BGA semiconductor package, the leads together with the base layer are used as a substrate for the semiconductor chip to attach thereto. Therefore, there is no need of costly BGA substrate.

摘要翻译： 具有暴露基层的球栅阵列（BGA）半导体封装包括在其中心具有开口部分并且围绕开口部分形成有多个孔的基层。 多个引线附接到基层的第二表面，并且每个引线连接到基层中的对应的孔。 半导体芯片被附接并电连接到引线。 半导体芯片和引线被由封装化合物形成的密封剂覆盖，留下基底层的第一表面露出。 多个焊球被种植在基底层的孔中，电焊接到引线上，以将半导体芯片电连接到外部装置。 在该BGA半导体封装中，将引线与基极层一起用作半导体芯片附着于其上的基板。 因此，不需要昂贵的BGA基板。

公开(公告)号：US06650009B2

公开(公告)日：2003-11-18

申请号：US10206720

申请日：2002-07-26

申请人： Tzong-Dar Her ,  Randy H. Y. Lo ,  Chien-Ping Huang

发明人： Tzong-Dar Her ,  Randy H. Y. Lo ,  Chien-Ping Huang

IPC分类号： H01L2302

CPC分类号： H01L23/3128 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A structure of a multi chip module package having stacked chips, having at least a substrate, a main chip, a plurality of chip sets, a plurality of spacers, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposite to the front surface. A plurality of chips are stacked in the form of laminate on the front surface of the substrate to form a plurality of chip sets, which are located next to the main chip. A plurality of spacers are arranged between each two adjacent chips. The connection between the spacers, the main chip, the chips, and the substrate are achieved by a plurality of glue layers. A plurality of wires are used to electrically connect the chips and the main chip to the substrate. Finally, the front surface of the substrate, the main chip, the spacers, the chips, and the glue layers are encapsulated with a mold compound to accomplish the package.

公开(公告)号：US06555902B2

公开(公告)日：2003-04-29

申请号：US09895553

申请日：2001-06-28

申请人： Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

发明人： Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

IPC分类号： H01L2302

CPC分类号： H01L25/0652 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00

摘要： A packaging structure comprises a substrate, a plurality of semiconductor chips contiguously mounted into a plurality of stacked semiconductor chip sets, a plurality of supporting members, a plurality of adhesive layers, a plurality of wires and a molding compound. Each of the semiconductor chip sets comprises at least a semiconductor chip, each semiconductor chip having plurality of bonding pads. The size deviation between the semiconductor chip sets is less than 0.3 mm. The supporting members separate from one another the semiconductor chip sets stacked above the substrate. The adhesive layers bond the substrate, the supporting members and the semiconductor chips to one another. The wires connect the semiconductor chips to one another and to the substrate. The molding compound encapsulates the substrate, the semiconductor chips, the supporting members, and the adhesive layers.

公开(公告)号：US06414384B1

公开(公告)日：2002-07-02

申请号：US09746793

申请日：2000-12-22

申请人： Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

发明人： Randy H. Y. Lo ,  Chien-Ping Huang ,  Chi-Chuan Wu

IPC分类号： H01L2302

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure stacking chips on a front surface and a back surface of a substrate including at least a substrate, a plurality of chip sets, a plurality of support members, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposite to the front surface. Each chip set has one or more chips, each chip having a plurality of bonding pads. The chip sets are stacked as a laminate on the front surface of the substrate, respectively. A plurality of support members are arranged between each two adjacent chip sets. A glue layers are used to connect the support members, the chip sets, and the substrate. The chip in the same chip sets is electrically connected to each other or to the substrate by the bonding pads. Finally, the front surface of the substrate, the support members, the chip sets, and the glue layers are encapsulated with a mold compound. Moreover, a plurality of flip chips are deposited on the back surface of the substrate.

摘要翻译： 一种封装结构，其在至少包括基板，多个芯片组，多个支撑部件，多个胶合层，多个导线和模具化合物的基板的前表面和背面上堆叠芯片。 基板具有与前表面相对的前表面和后表面。 每个芯片组具有一个或多个芯片，每个芯片具有多个焊盘。 芯片组分别作为层叠体堆叠在基板的前表面上。 在每个两个相邻的芯片组之间布置有多个支撑构件。 使用胶层来连接支撑部件，芯片组和基板。 相同芯片组中的芯片通过焊盘彼此电连接或与基板电连接。 最后，用模具化合物包封衬底的前表面，支撑构件，芯片组和胶层。 此外，在基板的背面上沉积多个倒装芯片。

公开(公告)号：US06306682B1

公开(公告)日：2001-10-23

申请号：US09547157

申请日：2000-04-11

申请人： Chien-Ping Huang ,  Randy H. Y. Lo ,  Tzong-Da Ho ,  Eric Ko ,  Jui-Meng Jao

发明人： Chien-Ping Huang ,  Randy H. Y. Lo ,  Tzong-Da Ho ,  Eric Ko ,  Jui-Meng Jao

IPC分类号： H01L2144

CPC分类号： H01L21/56 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A method of fabricating a BGA (Ball Grid Array) IC package of the type having an encapsulating body is proposed, which allows the BGA IC package to be manufactured without having to use conventional organic substrate and encapsulating-body mold having cavity, so that the manufacture process can be more cost-effective to carry out than the prior art. The proposed method is characterized in the use of a copper piece which is selectively removed to form an encapsulating-body cavity for the forming of an encapsulating body therein. The proposed method requires no use of mold with cavity for the forming of the encapsulating body, allowing the same mold to be used for the fabrication of various BGA IC packages of different sizes. Moreover, the proposed method allows fan-in design as well as fan-out design, thus allowing the number of I/O ports to be increased while making the overall package configuration compact in size, and also allows the implantation of the electrically-conductive balls to be easier to carry out and more precisely controlled than the prior art, making the ball implantation more assured in quality than the prior art. Therefore, the proposed method is more advantageous and cost-effective to use than the prior art.

摘要翻译： 提出了一种制造具有封装体的BGA（球栅阵列）IC封装的方法，其允许制造BGA IC封装，而不必使用传统的有机衬底和具有空腔的封装体模具， 制造工艺比现有技术更具成本效益。 所提出的方法的特征在于使用铜片，其被选择性地去除以形成用于在其中形成封装体的封装体腔体。 所提出的方法不需要使用具有空腔的模具来形成封装体，允许相同的模具用于制造不同尺寸的各种BGA IC封装。 此外，所提出的方法允许风扇设计以及扇出式设计，从而允许增加I / O端口的数量，同时使整个封装结构的尺寸紧凑，并且还允许将导电 球比现有技术更容易实施和更精确地控制，使得球注入在质量上比现有技术更加确保。 因此，所提出的方法比现有技术更有利且成本有效。

公开(公告)号：US06507120B2

公开(公告)日：2003-01-14

申请号：US09746819

申请日：2000-12-22

申请人： Randy H. Y. Lo ,  Chi-Chuan Wu

发明人： Randy H. Y. Lo ,  Chi-Chuan Wu

IPC分类号： H01L2348

CPC分类号： H01L23/4334 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A flip chip type quad flat non-leaded package, comprising: a plurality of leads each having a first surface and a second surface opposite to the first surface; a die having an active surface and a backside opposite the active surface, wherein the active surface has a plurality of bonding pads, each having a bump, and wherein each bump is connected to a first surface of one of the leads respectively; and a molding compound encapsulating the leads and the die, exposing second surfaces of the leads.

公开(公告)号：US06753609B2

公开(公告)日：2004-06-22

申请号：US09861425

申请日：2001-05-18

申请人： Feng-Lung Chien ,  Randy H. Y. Lo ,  Chun-chi Ke

发明人： Feng-Lung Chien ,  Randy H. Y. Lo ,  Chun-chi Ke

IPC分类号： H01L2348

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

摘要： A method is proposed for forming circuit probing (CP) contact points on fine pitch peripheral bond pads (PBP) on a flip chip for the purpose of facilitating peripheral circuit probing of the internal circuitry of the flip chip. The proposed method is characterized in the forming of a dual-layer NiV/Cu metallization structure, rather than a triple-layer Al/NiV/Cu metallization structure, over each aluminum-based PBP, which includes a bottom layer of nickel-vanadium (NiV) deposited over the aluminum-based PBP and an upper layer of copper (Cu) deposited over the nickel-vanadium layer. When low-resolution photolithographic and etching equipment is used for photoresist mask definition for selective removal of the NiV/Cu metallization structure, the resulted photoresist masking can be misaligned to the PBP. However, since no aluminum layer is included in the metallization structure, a Cu/NiV specific etchant would only etch away the copper layer and the nickel-vanadium layer but not the aluminum-based PBP, thus leaving the unmasked portion of the aluminum-based PBP intact.

摘要翻译： 提出了一种用于在倒装芯片上的细间距外围接合焊盘（PBP）上形成电路探测（CP）接触点的方法，其目的在于便于倒装芯片的内部电路的外围电路探测。 所提出的方法的特征在于在每个基于铝的PBP上形成双层NiV / Cu金属化结构而不是三层Al / NiV / Cu金属化结构，其包括镍 - 钒的底层（ NiV）沉积在铝基PBP上并沉积在镍 - 钒层上的铜（Cu）上层。 当低分辨率光刻和蚀刻设备用于光刻胶掩模定义以选择性去除NiV / Cu金属化结构时，所得到的光刻胶掩模可能不对准PBP。 然而，由于在金属化结构中不包括铝层，所以Cu / NiV特定蚀刻剂将仅蚀刻掉铜层和镍 - 钒层而不是铝基PBP，从而留下铝基的未掩模部分 PBP完好无损。

公开(公告)号：US06391758B1

公开(公告)日：2002-05-21

申请号：US09525717

申请日：2000-03-14

申请人： Randy H. Y. Lo ,  Jui-Meng Jao

发明人： Randy H. Y. Lo ,  Jui-Meng Jao

IPC分类号： H01L2144

CPC分类号： H01L23/49582 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/45099

摘要： A method is proposed for forming solder areas over a lead frame through deposition of an oxidation layer rather than selective removal of a polyimide-made solder mask, which allows the fabrication of the lead frame to be carried out in a more cost-effective and advantageous manner. The method allows the fabrication of the lead frame to be carried out through stamping without etching. Moreover, it can make the overall integrated circuit package less easily subjected to cracking and more securely assembled. Still moreover, it can make the overall integrated circuit package less likely to be weakened in structural strength by moisture. This method is therefore more advantageous to use than the prior art.

摘要翻译： 提出了通过沉积氧化层在引线框架上形成焊料区域而不是选择性去除聚酰亚胺制造的焊接掩模的方法，其允许以更具成本效益和有利的方式进行引线框架的制造 方式。 该方法允许通过冲压而不刻蚀来进行引线框架的制造。 此外，它可以使整个集成电路封装不易受到破裂的影响，并且更安全地组装。 此外，还可以使整体集成电路封装在结构强度的水分下不太可能被削弱。 因此，该方法比现有技术更有利于使用。

公开(公告)号：US06949413B2

公开(公告)日：2005-09-27

申请号：US10389138

申请日：2003-03-13

申请人： Randy H. Y. Lo ,  Chi-Chuan Wu

发明人： Randy H. Y. Lo ,  Chi-Chuan Wu

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/433 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate predefined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semiconductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package. In the foregoing process, since the entirety of the heat-spreader frame is relatively large in size as compared to the size of an individual TFBGA package, it can be easily handled, so that the embedding of a heat spreader in each package unit can be easily carried out.