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    POWER MODULE PACKAGE
    1.
    发明申请
    POWER MODULE PACKAGE 审中-公开
    电源模块封装

    公开(公告)号：US20170025379A1

    公开(公告)日：2017-01-26

    申请号：US15209777

    申请日：2016-07-14

    Applicant: DELTA ELECTRONICS, INC.

    Inventor： Le LIANG ,  Kai LU ,  Zhen-Qing ZHAO ,  Zeng LI

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

    CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/49838 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2924/1033 ,  H01L2924/1205 ,  H01L2924/13091 ,  H01L2924/15747

    Abstract: A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit board includes an insulating substrate and a conductive layer thereon. A bottom surface of the conductive layer touches a top surface of the insulating substrate. The insulating substrate has plural first openings to allow the conductive layer to be exposed from the bottom surface of the insulating substrate. The first electronic component is disposed on a top surface of the conductive layer. The second electronic component is disposed on the bottom surface of the insulating substrate and received in the first openings. The second electronic component is connected to the conductive layer via the first openings. At least one of the first electronic component and the second electronic component is a bare die.

    Abstract translation: 功率模块封装包括单层电路板，第一电子部件和第二电子部件。 单层电路板包括绝缘基板和导电层。 导电层的底表面接触绝缘基板的顶表面。 绝缘基板具有多个第一开口，以允许导电层从绝缘基板的底表面露出。 第一电子部件设置在导电层的顶表面上。 第二电子部件设置在绝缘基板的底面上并被接收在第一开口内。 第二电子部件经由第一开口连接到导电层。 第一电子部件和第二电子部件中的至少一个是裸模。

    SEMICONDUCTOR PACKAGING STRUCTURE AND SEMICONDUCTOR POWER DEVICE THEREOF
    2.
    发明申请
    SEMICONDUCTOR PACKAGING STRUCTURE AND SEMICONDUCTOR POWER DEVICE THEREOF 有权
    半导体封装结构和半导体功率器件

    公开(公告)号：US20160293755A1

    公开(公告)日：2016-10-06

    申请号：US15077927

    申请日：2016-03-23

    Applicant: DELTA ELECTRONICS, INC.

    Inventor： Chao-Feng CAI ,  Jian-Hong ZENG ,  Zeng LI

    IPC: H01L29/78 ,  H01L23/48 ,  H01L23/538 ,  H01L23/50

    CPC classification number: H01L29/7826 ,  H01L23/50 ,  H01L24/20 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/19104

    Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

    Abstract translation: 半导体封装结构包括芯片，第一引脚，第二引脚和第三引脚。 芯片包括第一表面，第二表面，第一电源开关和第二开关，并且第一电源开关和第二开关都包括第一端子和第二端子。 芯片的第二表面与芯片的第一表面相对。 第一个引脚不与第二个引脚接触。 芯片的第一电源开关的第一端子耦合到第一引脚，芯片的第一电源开关的第二端子耦合到第三引脚。 芯片的第二电源开关的第一端子耦合到第三引脚，芯片的第二电源开关的第二端子耦合到第二引脚。

    SEMICONDUCTOR PACKAGING STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR PACKAGING STRUCTURE 审中-公开

    公开(公告)号：US20190296150A1

    公开(公告)日：2019-09-26

    申请号：US16436939

    申请日：2019-06-11

    Applicant: DELTA ELECTRONICS, INC.

    Inventor： Chao-Feng CAI ,  Jian-Hong ZENG ,  Zeng LI ,  Xiao-Ni XIN

    IPC: H01L29/78 ,  H01L23/50 ,  H01L23/00

    Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

    CASCODE SWITCH DEVICE AND VOLTAGE PROTECTION METHOD
    5.
    发明申请
    CASCODE SWITCH DEVICE AND VOLTAGE PROTECTION METHOD 有权
    CASCODE开关装置和电压保护方法

    公开(公告)号：US20160181788A1

    公开(公告)日：2016-06-23

    申请号：US14813140

    申请日：2015-07-30

    Applicant: DELTA ELECTRONICS, INC.

    Inventor： Zeng LI ,  Chao-Feng CAI

    IPC: H02H3/28 ,  H03K17/687

    CPC classification number: H03K17/0828 ,  H03K17/567 ,  H03K17/6871 ,  H03K2017/6875

    Abstract: A cascode switch device includes a cascode circuit, which includes a first switch and a second switch, and a protection circuit. The protection circuit is coupled between the first switch and the second switch. A first leakage current passing through the protection circuit is greater than or equal to a difference between a second leakage current and a third leakage current, and is smaller than an upper limit value of a leakage current of the cascode circuit. An upper limit value of a withstanding voltage is present between the first terminal and the control terminal of the first switch. When the first switch operates at the upper limit value of the withstanding voltage, the second leakage current is an upper limit value of a leakage current passing through the first switch, and the third leakage current is a lower limit value of a leakage current passing through the second switch.

    Abstract translation: 共射共同开关装置包括共源共栅电路，其包括第一开关和第二开关以及保护电路。 保护电路耦合在第一开关和第二开关之间。 通过保护电路的第一漏电流大于或等于第二泄漏电流和第三漏电流之间的差，并且小于共源共栅电路的漏电流的上限值。 在第一开关的第一端子和控制端子之间存在耐受电压的上限值。 当第一开关工作在耐受电压的上限值时，第二漏电流是通过第一开关的漏电流的上限值，第三漏电流是通过的漏电流的下限值 第二个开关。

    LAYOUT OF POWER CONVERTER
    6.
    发明申请
    LAYOUT OF POWER CONVERTER 有权
    电源转换器布局

    公开(公告)号：US20160173000A1

    公开(公告)日：2016-06-16

    申请号：US14962074

    申请日：2015-12-08

    Applicant: DELTA ELECTRONICS,INC.

    Inventor： Juncheng LU ,  Zeng LI

    IPC: H02M7/5387 ,  H02M7/06

    CPC classification number: H02M7/003 ,  H02M7/538 ,  H02M7/797

    Abstract: A layout of a switching power converter, wherein the switching power converter includes: a capacitor unit receiving or outputting DC voltage; six power transistor units transforming the DC voltage to the AC voltage or the AC voltage to the DC voltage; and a carrier board with the capacitor unit and the six power transistor units on. The layout of the switching power converter includes a first commutation loop and a second commutation loop, in which the six power transistor units are arranged on the same surface of the carrier board. In order to ensure the first commutation loop and the second commutation loop as short as possible, the fifth power transistor unit is located at a middle position of the carrier board, surrounded by the other five power transistor units as closely as possible.

    Abstract translation: 一种开关电源转换器的布局，其中开关电源转换器包括：接收或输出直流电压的电容器单元; 六个功率晶体管单元将DC电压转换为AC电压或AC电压至DC电压; 和带有电容器单元和六个功率晶体管单元的载板。 开关功率转换器的布局包括第一换向环和第二换向环，其中六个功率晶体管单元布置在载板的同一表面上。 为了确保第一换向回路和第二换向回路尽可能短，第五功率晶体管单元位于载板的中间位置，由其它五个功率晶体管单元尽可能靠近地围绕。

    POWER SWITCH CIRCUIT
    8.
    发明申请
    POWER SWITCH CIRCUIT 有权
    电源开关电路

    公开(公告)号：US20160314914A1

    公开(公告)日：2016-10-27

    申请号：US14959071

    申请日：2015-12-04

    Applicant: DELTA ELECTRONICS, INC.

    Inventor： Zeng LI ,  Chaofeng CAI

    IPC: H01H9/54

    CPC classification number: H02M3/158 ,  H02M2001/0054 ,  Y02B70/1491

    Abstract: A power switch circuit includes at least one switch unit including at least one first switch and one second switch which are connected in parallel. A turning-on loss of the first switch is smaller than a turning-on loss of the second switch, a turning-off loss of the first switch is larger than a turning-off loss of the second switch; during one controlling period of the switch unit, when the switch unit is controlled to be turned on, a moment when the first switch is turned on is controlled to be earlier than a moment when the second switch is turned on; and when the switch unit is controlled to be turned off, a moment when the first switch is turned off is controlled to be earlier than a moment when the second switch is turned off.

    Abstract translation: 电源开关电路包括至少一个开关单元，其包括并联连接的至少一个第一开关和一个第二开关。 第一开关的导通损耗小于第二开关的导通损耗，第一开关的断开损耗大于第二开关的关断损耗; 在开关单元的一个控制周期期间，当开关单元被控制为接通时，第一开关接通的时刻被控制为比第二开关接通时的时刻早; 并且当开关单元被控制为关闭时，第一开关关闭的时刻被控制为比第二开关关闭的时刻早。

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