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公开(公告)号：US06426470B1
公开(公告)日：2002-07-30
申请号：US09764464
申请日：2001-01-17
IPC分类号： H05K111
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
摘要翻译： 涉及多段电镀通孔的方法和结构。 基板包括夹在第一层叠层和第二层叠层之间的电介质层。 穿过基板形成通孔。 通孔穿过介电层内的不可电介质材料。 结果，随后的通孔的接种和电镀导致在第一层压层的段上的通孔的壁上和第二层压层的段上形成导电金属电镀，而不在不可电绝缘的电介质 电介质层的材料。 因此，导电金属电镀从第一层叠层到第二层叠层不是连续的。
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公开(公告)号：US06996903B2
公开(公告)日：2006-02-14
申请号：US10641182
申请日：2003-08-14
IPC分类号： H01K3/10
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
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公开(公告)号：US06700078B2
公开(公告)日：2004-03-02
申请号：US10176254
申请日：2002-06-19
IPC分类号： H05K116
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
摘要翻译： 涉及多段电镀通孔的方法和结构。 基板包括夹在第一层叠层和第二层叠层之间的电介质层。 穿过基板形成通孔。 通孔穿过介电层内的不可电介质材料。 结果，随后的通孔的接种和电镀导致在第一层压层的段上的通孔的壁上和第二层压层的段上形成导电金属电镀，而不在不可电绝缘的电介质 电介质层的材料。 因此，导电金属电镀从第一层叠层到第二层叠层不是连续的。
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公开(公告)号：US06343001B1
公开(公告)日：2002-01-29
申请号：US09655381
申请日：2000-09-05
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4611 , H05K3/4641 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , H05K2203/0759
摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.
摘要翻译： 提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。 通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。 第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。 在第一和第二外部平面的每一个中形成至少一个间隙孔。 可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。 本发明还涉及通过这些方法形成的结构。
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5.发明授权Multilayer capacitance structure and circuit board containing the same and method of forming the same 有权多层电容结构和电路板含有相同的方法和其形成方法公开(公告)号：US06496356B2
公开(公告)日：2002-12-17
申请号：US10026873
申请日：2001-12-21
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4611 , H05K3/4641 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , H05K2203/0759
摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.
摘要翻译： 提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。 通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。 第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。 在第一和第二外部平面的每一个中形成至少一个间隙孔。 可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。 本发明还涉及通过这些方法形成的结构。
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公开(公告)号：US07076869B2
公开(公告)日：2006-07-18
申请号：US10260153
申请日：2002-09-27
IPC分类号： H01K3/10
CPC分类号： H05K3/462 , H05K3/321 , H05K3/423 , H05K3/4623 , H05K2201/09536 , H05K2201/09563 , H05K2201/096 , H05K2203/0733 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： The present invention relates to a method for providing an interconnect between layers of a multilayer circuit board. A first via extending through a total thickness of a first layer is formed. The first via is totally filled with a first solid conductive plug and an end of the first solid conductive plug includes a first contact pad that is in contact with a surface of the first layer. A second via extending through a total thickness of a second layer is formed. The second via totally filling with a second solid conductive plug and an end of the second solid conductive plug includes a second contact pad that is in contact with a surface of the second layer. The second layer is electrically and mechanically coupled to the first layer by an electrically conductive adhesive that is in electrical and mechanical contact with both the end of the first plug and the end of the second plug.
摘要翻译： 本发明涉及一种在多层电路板的层之间提供互连的方法。 形成延伸通过第一层的总厚度的第一通孔。 第一通孔完全填充有第一固体导电插塞，并且第一固体导电插塞的端部包括与第一层的表面接触的第一接触垫。 形成延伸穿过第二层的总厚度的第二通孔。 通过完全填充第二固体导电插塞和第二固体导电插塞的端部的第二通孔包括与第二层的表面接触的第二接触垫。 第二层通过与第一插头的端部和第二插头的端部电接触和机械接触的导电粘合剂电和机械地耦合到第一层。
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公开(公告)号：US07014731B2
公开(公告)日：2006-03-21
申请号：US09781730
申请日：2001-02-12
IPC分类号： C09J5/02
CPC分类号： H05K1/036 , H01L2224/16 , H01L2924/15311 , H05K1/0269 , H05K1/034 , H05K1/0373 , H05K3/386 , H05K2201/0116 , H05K2201/015 , H05K2201/0209 , H05K2203/122 , H05K2203/161 , Y10T428/24917 , Y10T428/249958 , Y10T428/25 , Y10T428/252 , Y10T428/256 , Y10T428/31544
摘要： A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material is a non-fibrillated, fluoropolymer matrix that has inorganic particles distributed therein and is impregnated with a thermoset material.
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公开(公告)号：US06686539B2
公开(公告)日：2004-02-03
申请号：US09753932
申请日：2001-01-03
申请人： Donald S. Farquhar , Claudius Feger , Voya Markovich , Konstantinos I. Papathomas , Mark D. Poliks , Jane M. Shaw , George Szeparowycz , Steve H. Weingart
发明人： Donald S. Farquhar , Claudius Feger , Voya Markovich , Konstantinos I. Papathomas , Mark D. Poliks , Jane M. Shaw , George Szeparowycz , Steve H. Weingart
IPC分类号： H05K506
CPC分类号： H01L23/57 , G06F21/87 , H01L2924/0002 , H05K1/0275 , H05K1/0393 , H05K1/095 , H05K1/167 , H05K2201/0352 , H05K2201/10151 , H05K2203/1572 , H01L2924/00
摘要： A structure and method for forming a tamper respondent electronic circuit enclosure that includes an integrated circuit structure, a mesh structure surrounding the integrated circuit structure, and a sealed enclosure surrounding the mesh structure. The mesh structure includes a layer of flexible dielectric having a first side and a second side, a screen-printed pattern of flexible electrically conductive first circuit lines forming a first resistor network on the first side, and a photo lithographically-formed pattern of flexible electrically conductive second circuit lines forming a second resistor network on the second side.
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9.发明授权公开(公告)号：US06465084B1
公开(公告)日：2002-10-15
申请号：US09834281
申请日：2001-04-12
IPC分类号： B32B300
CPC分类号： H05K3/462 , H05K3/386 , H05K3/4069 , H05K3/4623 , H05K3/4641 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/0353 , H05K2203/0384 , H05K2203/0554 , H05K2203/063 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T428/24917
摘要： A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.
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10.发明授权Method and article for filling apertures in a high performance electronic substrate 失效用于在高性能电子基板中填充孔的方法和制品公开(公告)号：US06429527B1
公开(公告)日：2002-08-06
申请号：US09764047
申请日：2001-01-17
IPC分类号： H01L2978
CPC分类号： H01L21/486 , H01L23/49883 , H01L2924/0002 , H05K3/0094 , H05K3/4069 , H05K3/4602 , H05K2201/0347 , H05K2201/0959 , H05K2203/0152 , H05K2203/0156 , H05K2203/0278 , H05K2203/0338 , H05K2203/0554 , H05K2203/1461 , H01L2924/00
摘要： The present invention provides a method of filling an at least one aperture in a semiconductor substrate by placing a sacrificial carrier structure on a surface of the substrate, wherein the structure comprises, a first layer, a fill material over the first layer, and a mask over fill material having at least one opening therein, such that the opening at least partially aligns with the aperture in the substrate. Thereafter, the fill material is forced into the aperture by the application of heat and pressure, and the sacrificial carrier structure is removed.
摘要翻译： 本发明提供了一种通过在衬底的表面上放置牺牲载体结构来填充半导体衬底中的至少一个孔的方法，其中该结构包括第一层，第一层上的填充材料和掩模 在其中具有至少一个开口的过填充材料，使得该开口至少部分地与衬底中的孔对准。 此后，通过施加热和压力将填充材料压入孔中，并去除牺牲载体结构。
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