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公开(公告)号：US06426470B1
公开(公告)日：2002-07-30
申请号：US09764464
申请日：2001-01-17
IPC分类号： H05K111
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
摘要翻译： 涉及多段电镀通孔的方法和结构。 基板包括夹在第一层叠层和第二层叠层之间的电介质层。 穿过基板形成通孔。 通孔穿过介电层内的不可电介质材料。 结果，随后的通孔的接种和电镀导致在第一层压层的段上的通孔的壁上和第二层压层的段上形成导电金属电镀，而不在不可电绝缘的电介质 电介质层的材料。 因此，导电金属电镀从第一层叠层到第二层叠层不是连续的。
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公开(公告)号：US06343001B1
公开(公告)日：2002-01-29
申请号：US09655381
申请日：2000-09-05
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4611 , H05K3/4641 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , H05K2203/0759
摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.
摘要翻译： 提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。 通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。 第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。 在第一和第二外部平面的每一个中形成至少一个间隙孔。 可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。 本发明还涉及通过这些方法形成的结构。
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公开(公告)号：US06996903B2
公开(公告)日：2006-02-14
申请号：US10641182
申请日：2003-08-14
IPC分类号： H01K3/10
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
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4.发明授权Multilayer capacitance structure and circuit board containing the same and method of forming the same 有权多层电容结构和电路板含有相同的方法和其形成方法公开(公告)号：US06496356B2
公开(公告)日：2002-12-17
申请号：US10026873
申请日：2001-12-21
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4611 , H05K3/4641 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , H05K2203/0759
摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.
摘要翻译： 提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。 通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。 第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。 在第一和第二外部平面的每一个中形成至少一个间隙孔。 可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。 本发明还涉及通过这些方法形成的结构。
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公开(公告)号：US06700078B2
公开(公告)日：2004-03-02
申请号：US10176254
申请日：2002-06-19
IPC分类号： H05K116
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
摘要翻译： 涉及多段电镀通孔的方法和结构。 基板包括夹在第一层叠层和第二层叠层之间的电介质层。 穿过基板形成通孔。 通孔穿过介电层内的不可电介质材料。 结果，随后的通孔的接种和电镀导致在第一层压层的段上的通孔的壁上和第二层压层的段上形成导电金属电镀，而不在不可电绝缘的电介质 电介质层的材料。 因此，导电金属电镀从第一层叠层到第二层叠层不是连续的。
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6.发明申请公开(公告)号：US20130033827A1
公开(公告)日：2013-02-07
申请号：US13198756
申请日：2011-08-05
申请人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
发明人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
CPC分类号： H05K1/0313 , B23K26/382 , B23K26/40 , B23K2101/40 , B23K2103/16 , B23K2103/172 , B23K2103/52 , H01B1/22 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311 , H05K1/097 , H05K3/4053 , H05K3/4069 , H05K3/462 , H05K3/4623 , H05K3/4641 , H05K2201/0257 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0425 , H05K2203/1152 , Y10T29/49128 , Y10T29/49165 , H01L2924/00
摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
摘要翻译： 用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。 具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。 导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。
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7.发明授权公开(公告)号：US06479093B2
公开(公告)日：2002-11-12
申请号：US10062100
申请日：2002-01-31
申请人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
IPC分类号： B05D512
CPC分类号： H05K3/462 , H01R4/26 , H05K3/0023 , H05K3/4069 , H05K3/4623 , H05K3/4641 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/0307 , Y10S428/901 , Y10T156/1089 , Y10T428/24917
摘要： A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.
摘要翻译： 提供了一种层叠电路结构组件，其包括至少两个模块化电路化的平面子组件; 位于每个子组件之间的接合层，并且其中所述子组件和接合层与来自可结合的可固化电介质的固化电介质结合在一起。 子组件和接合层与可结合的导电材料电互连。 接合层包括围绕内部导电层设置的电介质层。 导电层具有通孔，并且介电层各自具有比导电层中的通孔更小的直径的通孔，并且与导电层中的通孔对准。 通孔填充有电可焊接的导电材料，用于在子组件之间提供电接触。
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8.发明授权公开(公告)号：US09451693B2
公开(公告)日：2016-09-20
申请号：US13198756
申请日：2011-08-05
申请人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
发明人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
CPC分类号： H05K1/0313 , B23K26/382 , B23K26/40 , B23K2101/40 , B23K2103/16 , B23K2103/172 , B23K2103/52 , H01B1/22 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311 , H05K1/097 , H05K3/4053 , H05K3/4069 , H05K3/462 , H05K3/4623 , H05K3/4641 , H05K2201/0257 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0425 , H05K2203/1152 , Y10T29/49128 , Y10T29/49165 , H01L2924/00
摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
摘要翻译： 用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。 具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。 导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。
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公开(公告)号：US06388204B1
公开(公告)日：2002-05-14
申请号：US09651010
申请日：2000-08-29
申请人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
IPC分类号： H01R909
CPC分类号： H05K3/462 , H01R4/26 , H05K3/0023 , H05K3/4069 , H05K3/4623 , H05K3/4641 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/0307 , Y10S428/901 , Y10T156/1089 , Y10T428/24917
摘要： A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.
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公开(公告)号：US06593534B2
公开(公告)日：2003-07-15
申请号：US09812261
申请日：2001-03-19
申请人： Gerald W. Jones , John M. Lauffer , Voya R. Markovich , Thomas R. Miller , James P. Paoletti , Konstantinos I. Papathomas , James R. Stack
发明人： Gerald W. Jones , John M. Lauffer , Voya R. Markovich , Thomas R. Miller , James P. Paoletti , Konstantinos I. Papathomas , James R. Stack
IPC分类号： H01R909
CPC分类号： H05K3/462 , H05K1/115 , H05K3/4069 , H05K2201/0347 , H05K2201/0352 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2203/0554
摘要： A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.
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