公开(公告)号：US06964889B2

公开(公告)日：2005-11-15

申请号：US10137081

申请日：2002-05-01

申请人： Qing Ma ,  Xiao-Chun Mu ,  Quat T. Vu

发明人： Qing Ma ,  Xiao-Chun Mu ,  Quat T. Vu

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L21/44

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

公开(公告)号：US06902950B2

公开(公告)日：2005-06-07

申请号：US10143340

申请日：2002-05-10

申请人： Qing Ma ,  Xiao-Chun Mu ,  Quat T. Vu

发明人： Qing Ma ,  Xiao-Chun Mu ,  Quat T. Vu

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L21/44

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

摘要翻译： 一种微电子封装，其包括具有活性表面和至少一个侧面的微电子管芯。 封装材料邻近微电子管芯侧设置。 去除包封材料的一部分以露出其上设置有金属化层的微电子管芯的背面。 在封装之前，保护层设置在金属化层上，使得当去除封装材料的部分时，保护层防止金属化层被损坏。 在去除封装材料的部分之后，去除保护层并暴露金属化层。 然后可以通过使散热器抵靠金属化层并且回流金属化层而将散热器附接到微电子管芯。

公开(公告)号：US06586822B1

公开(公告)日：2003-07-01

申请号：US09658819

申请日：2000-09-08

申请人： Quat T. Vu ,  Jian Li ,  Qing Ma ,  Maria V. Henao ,  Xiao-Chun Mu

发明人： Quat T. Vu ,  Jian Li ,  Qing Ma ,  Maria V. Henao ,  Xiao-Chun Mu

IPC分类号： H01L2302

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L23/532 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  Y10T29/4935 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

摘要： A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

摘要翻译： 一种微电子封装，包括设置在微电子封装芯中的开口内的微电子管芯，其中封装材料设置在不被微电子管芯占据的开口部分内。 然后在微电子管芯，密封剂材料和微电子封装芯上制造介电材料和导电迹线的堆积层以形成微电子封装。

公开(公告)号：US06423570B1

公开(公告)日：2002-07-23

申请号：US09691738

申请日：2000-10-18

申请人： Qing Ma ,  Xiao-Chun Mu ,  Quat T. Vu

发明人： Qing Ma ,  Xiao-Chun Mu ,  Quat T. Vu

IPC分类号： H01L2144

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

摘要翻译： 一种微电子封装，其包括具有活性表面和至少一个侧面的微电子管芯。 封装材料邻近微电子管芯侧设置。 去除包封材料的一部分以露出其上设置有金属化层的微电子管芯的背面。 在封装之前，保护层设置在金属化层上，使得当去除封装材料的部分时，保护层防止金属化层被损坏。 在去除封装材料的部分之后，去除保护层并暴露金属化层。 然后可以通过使散热器抵靠金属化层并且回流金属化层而将散热器附接到微电子管芯。

公开(公告)号：US06586836B1

公开(公告)日：2003-07-01

申请号：US09516652

申请日：2000-03-01

申请人： Qing Ma ,  Xiao-Chun Mu ,  Quat Vu ,  Steve Towle

发明人： Qing Ma ,  Xiao-Chun Mu ,  Quat Vu ,  Steve Towle

IPC分类号： H01L2348

CPC分类号： H01L24/19 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/92144 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

摘要： A method of fabricating microelectronic dice by providing or forming a first encapsulated die assembly and a second encapsulated die assembly. Each of the encapsulated die assemblies includes at least one microelectronic die disposed in an encapsulation material. Each of the encapsulated die assemblies has an active surface and a back surface. The encapsulated die assemblies are attached together in a back surface-to-back surface arrangement. Build-up layers are then formed on the active surfaces of the first and second encapsulated assemblies, preferably, simultaneously. Thereafter, the microelectronic dice are singulated, if required, and the microelectronic dice of the first encapsulated die assembly are separated from the microelectronic dice of the second encapsulated die assembly.

摘要翻译： 一种通过提供或形成第一封装模具组件和第二封装模具组件来制造微电子模具的方法。 每个封装的管芯组件包括设置在封装材料中的至少一个微电子管芯。 每个封装的模具组件具有活性表面和后表面。 封装的模头组件以后表面对背表面布置连接在一起。 然后，优选地，同时地，在第一和第二封装组件的活性表面上形成积层。 此后，如果需要，微电子骰子是单切的，并且第一封装模具组件的微电子骰子与第二封装模具组件的微电子骰子分开。

公开(公告)号：US06524887B2

公开(公告)日：2003-02-25

申请号：US09909529

申请日：2001-07-20

申请人： Jian Li ,  Xiao-Chun Mu

发明人： Jian Li ,  Xiao-Chun Mu

IPC分类号： H01L2144

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C11/22 ,  H01L23/057 ,  H01L23/08 ,  H01L24/45 ,  H01L24/48 ,  H01L27/11502 ,  H01L27/118 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to packaging of a novel ferroelectric polymer memory device. Packaging is configured with a recess geometry into which the ferroelectric polymer memory device extends, that resists contact with the polymer portion of the ferroelectric polymer memory device. In one embodiment, an embedded recess geometry is used that resists thermal and mechanical stresses upon the polymer. Also disclosed is a method of forming the ferroelectric polymer memory device. The method may be applied to both inorganic and organic substrates.

摘要翻译： 本发明涉及新型铁电聚合物存储器件的封装。 包装被构造为具有凹槽几何形状，铁电聚合物存储器件延伸到该凹槽几何形状中，其抵抗与铁电聚合物存储器件的聚合物部分的接触。 在一个实施例中，使用嵌入式凹槽几何形状来抵抗聚合物上的热和机械应力。还公开了形成铁电聚合物存储器件的方法。 该方法可以应用于无机和有机衬底。

公开(公告)号：US06461954B1

公开(公告)日：2002-10-08

申请号：US09929408

申请日：2001-08-14

申请人： Jian Li ,  Xiao-Chun Mu ,  Sridhar Balakrishnan

发明人： Jian Li ,  Xiao-Chun Mu ,  Sridhar Balakrishnan

IPC分类号： H01L2130

CPC分类号： H01L23/485 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  Y10T428/12479 ,  Y10T428/12556 ,  Y10T428/12583 ,  Y10T428/12743 ,  Y10T428/12812 ,  Y10T428/31678 ,  H01L2224/05552

摘要： Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350° C. to approximately 550° C.

公开(公告)号：US06365962B1

公开(公告)日：2002-04-02

申请号：US09538327

申请日：2000-03-29

申请人： Chunlin Liang ,  Larry Eugene Mosley ,  Xiao-Chun Mu

发明人： Chunlin Liang ,  Larry Eugene Mosley ,  Xiao-Chun Mu

IPC分类号： H01L23495

CPC分类号： H01L25/18 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4623 ,  H01L2924/00 ,  H01L2224/0401

摘要： According to an embodiment of the invention, an integrated circuit (IC) package is provided that includes a flexible circuit board that has a first surface and a second surface. An integrated circuit mounted to the first surface of the flexible circuit board is provided. An electrical element is attached to the second surface of the flexible circuit board. Also, an encapsulant is attached to the flexible circuit board and the integrated circuit. The flexible circuit board includes at least one layer of dielectric that is no greater than approximately 35 microns thick. In another embodiment, the integrated circuit and the electrical element may be interchanged. A method is provided including attaching an encapsulant to an IC, forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, and attaching the substrate to the encapsulant so that the substrate is connected to the IC. Also, an electrical element may be attached with a flip-chip C4 (controlled collapsed chip connection) process.

摘要翻译： 根据本发明的实施例，提供了一种集成电路（IC）封装，其包括具有第一表面和第二表面的柔性电路板。 提供安装到柔性电路板的第一表面的集成电路。 电元件附接到柔性电路板的第二表面。 此外，密封剂附接到柔性电路板和集成电路。 柔性电路板包括不大于约35微米厚的至少一层电介质。 在另一个实施例中，集成电路和电气元件可以互换。 提供了一种方法，包括将密封剂附着到IC，从至少一层电介质形成衬底，将至少一个电接触附接到衬底，以及将衬底附接到密封剂，使得衬底连接到IC。 此外，电元件可以用倒装芯片C4（受控的塌陷芯片连接）工艺附接。

公开(公告)号：US5035768A

公开(公告)日：1991-07-30

申请号：US560988

申请日：1990-07-30

申请人： Xiao-Chun Mu ,  Jagir Multani

发明人： Xiao-Chun Mu ,  Jagir Multani

IPC分类号： C23F4/00 ,  H01L21/3213 ,  H01L21/768

CPC分类号： C23F4/00 ,  H01L21/32136 ,  H01L21/7684

摘要： An etchback process for etching a refractory metal layer formed on a semiconductor substrate with a greatly reduced micro-loading effect. The etch proceeds in three steps. The first step is a uniform etch which utilizes a gas chemistry of SF.sub.6, O.sub.2 and He and proceeds for a predetermined time to remove most of the metal layer. The second step is a very uniform etch which utilizes a gas chemistry of SF.sub.6, Cl.sub.2 and He and proceeds until the endpoint is detected. The endpoint is detected by measurement and integration of the 772 nm and 775 nm lines of Cl. The third step is a timed etch utilizing a gas chemistry of Cl.sub.2 and He which is used as both an overetch to ensure complete removal of the refractory metal film and as a selective etchant to remove an adhesion underlayer.

摘要翻译： 用于蚀刻形成在半导体衬底上的难熔金属层，具有大大降低的微负载效应的回蚀工艺。 蚀刻在三个步骤中进行。 第一步是使用SF6，O2和He的气体化学物质的均匀蚀刻，并且进行预定时间以去除大部分金属层。 第二步是使用SF6，Cl2和He的气体化学物质的非常均匀的蚀刻，并继续进行直到检测到端点。 通过测量和整合Cl的772nm和775nm线来检测终点。 第三步是利用Cl2和He的气体化学进行的定时蚀刻，其用作保护完全去除难熔金属膜的过滤材料，以及作为去除粘附底层的选择性蚀刻剂。

公开(公告)号：US06960479B2

公开(公告)日：2005-11-01

申请号：US09960125

申请日：2001-09-21

申请人： Jian Li ,  Xiao-Chun Mu

发明人： Jian Li ,  Xiao-Chun Mu

IPC分类号： G11C11/22 ,  H01L21/00 ,  H01L27/28 ,  H01L31/113 ,  H01L31/119 ,  H01R4/24 ,  H01R13/648 ,  H01R33/02 ,  H01R39/00

CPC分类号： G11C11/22 ,  B82Y10/00 ,  H01L27/285

摘要： The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures. Combining ferroelectric polymer and ferroelectric oxide layers on the pre-fabricated silicon substrate cavity forms a multi-rank structure.

摘要翻译： 铁电聚合物储存装置技术领域本发明涉及一种铁电聚合物储存装置，其包括至少两个层叠的铁电聚合物存储结构，它们被排列在至少两个相应堆叠的拓扑结构之上，该拓扑结构是包括层间电介质层和通孔结构的预制硅衬底腔。 在预制的硅衬底空腔上组合铁电聚合物和铁电氧化物层形成多级结构。