公开(公告)号：US06503821B2

公开(公告)日：2003-01-07

申请号：US10006229

申请日：2001-12-10

申请人： Donald Seton Farquhar ,  Lisa Jeanine Jimarez ,  Michael Joseph Klodowski ,  Jeffrey Alan Zimmerman

发明人： Donald Seton Farquhar ,  Lisa Jeanine Jimarez ,  Michael Joseph Klodowski ,  Jeffrey Alan Zimmerman

IPC分类号： H01L2144

CPC分类号： H01L25/0655 ,  H01L23/49816 ,  H01L23/5387 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit chip carrier assembly is provided by joining a substrate having electrically conductive regions on at least one major surface thereof to a stiffener by a bonding film. The bonding film comprises a dielectric substrate having a thermoset adhesive on both of its major surfaces. The thermoset adhesive prior to the bonding is a B-stage adhesive, is tack-free at normal room temperatures and is solvent free.

公开(公告)号：US06329713B1

公开(公告)日：2001-12-11

申请号：US09176654

申请日：1998-10-21

申请人： Donald Seton Farquhar ,  Lisa Jeanine Jimarez ,  Michael Joseph Klodowski ,  Jeffrey Alan Zimmerman

发明人： Donald Seton Farquhar ,  Lisa Jeanine Jimarez ,  Michael Joseph Klodowski ,  Jeffrey Alan Zimmerman

IPC分类号： H01L2308

CPC分类号： H01L25/0655 ,  H01L23/49816 ,  H01L23/5387 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit chip carrier assembly is provided by joining a substrate having electrically conductive regions on at least one major surface thereof to a stiffener by a bonding film. The bonding film comprises a dielectric substrate having a thermoset adhesive on both of its major surfaces. The thermoset adhesive prior to the bonding is a B-stage adhesive, is tack-free at normal room temperatures and is solvent free.

摘要翻译： 通过将具有至少一个主表面上的导电区域的基板通过接合膜连接到加强件来提供集成电路芯片载体组件。 接合膜包括在其主表面上具有热固性粘合剂的电介质基底。 在粘合之前的热固性粘合剂是B阶粘合剂，在正常室温下是无粘性的并且是无溶剂的。

公开(公告)号：US06369449B2

公开(公告)日：2002-04-09

申请号：US09228601

申请日：1999-01-12

申请人： Donald Seton Farquhar ,  Michael Joseph Klodowski ,  Kostantinos Papathomas ,  James Robert Wilcox

发明人： Donald Seton Farquhar ,  Michael Joseph Klodowski ,  Kostantinos Papathomas ,  James Robert Wilcox

IPC分类号： H01L2348

CPC分类号： H01L23/3128 ,  H01L21/54 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599

摘要： The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

摘要翻译： 由附接到基板的集成电路芯片组成的集成电路芯片组件的电气连接通过将密封剂材料通过基板中的开口分配到集成电路芯片与集成电路芯片之间的空间中而被高粘度密封剂材料封装并增强 基质。 制造具有加强电互连的集成电路芯片组件，其由于集成电路芯片与集成电路芯片所附接的基板之间的热膨胀系数的差异而产生的应力结果，更能抵抗弱化。

公开(公告)号：US06902869B2

公开(公告)日：2005-06-07

申请号：US10664996

申请日：2003-09-17

申请人： Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

发明人： Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

IPC分类号： H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/02 ,  H05K3/10

CPC分类号： H05K3/4007 ,  H05K3/06 ,  H05K3/20 ,  H05K3/427 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1572 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

摘要翻译： 一种形成多个固体导电凸块的方法，用于将电路板的两个导电层与基本上共面的上表面互连。 该方法包括以下步骤：将连续的均质金属层施加到电介质基底上，施加第一光致抗蚀剂并暴露和显影所述第一光致抗蚀剂以限定导电凸块的图案; 蚀刻由所述显影暴露的金属层以形成所述多个导电凸块; 去除所述第一光致抗蚀剂; 在所述金属层上施加第二光致抗蚀剂; 曝光和显影所述第二光致抗蚀剂以限定导电凸块和电路线的图案; 蚀刻由所述显影曝光的金属层，以在所述金属层中形成电路线图案; 并除去所述第二光致抗蚀剂。 本发明的方法还提供制造用于向面板提供刚性的多层电路板和金属边框。

公开(公告)号：US06684497B2

公开(公告)日：2004-02-03

申请号：US09789156

申请日：2001-02-20

申请人： Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

发明人： Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

IPC分类号： H01K310

CPC分类号： H05K3/4007 ,  H05K3/06 ,  H05K3/20 ,  H05K3/427 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1572 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of forming a printed circuit board comprising a plurality of conductive bumps with substantially coplanar upper surfaces. The method comprises the steps of applying a metal layer onto a dielectric substrate; applying a first photoresist onto said substrate and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The present invention is also provides a method for preparing a reinforced panel.

摘要翻译： 一种形成印刷电路板的方法，该印刷电路板包括具有基本上共面的上表面的多个导电凸块。 该方法包括以下步骤：将金属层施加到电介质基片上; 将第一光致抗蚀剂施加到所述基底上并暴露和显影所述第一光致抗蚀剂以限定导电凸块的图案; 蚀刻由所述显影暴露的金属层以形成所述多个导电凸块; 去除所述第一光致抗蚀剂; 在所述金属层上施加第二光致抗蚀剂; 曝光和显影所述第二光致抗蚀剂以限定导电凸块和电路线的图案; 蚀刻由所述显影曝光的金属层，以在所述金属层中形成电路线图案; 并除去所述第二光致抗蚀剂。 本发明还提供一种制备增强板的方法。

公开(公告)号：US06570261B2

公开(公告)日：2003-05-27

申请号：US10118395

申请日：2002-04-08

申请人： Donald Seton Farquhar ,  Michael Joseph Klodowski ,  Konstantinos Papathomas ,  James Robert Wilcox

发明人： Donald Seton Farquhar ,  Michael Joseph Klodowski ,  Konstantinos Papathomas ,  James Robert Wilcox

IPC分类号： H01L2348

CPC分类号： H01L23/3128 ,  H01L21/54 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599

摘要： The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

公开(公告)号：US06534724B1

公开(公告)日：2003-03-18

申请号：US08864044

申请日：1997-05-28

申请人： Donald Seton Farquhar ,  Gerard Paul Kohut ,  Andrew Michael Seman ,  Michael Joseph Klodowski

发明人： Donald Seton Farquhar ,  Gerard Paul Kohut ,  Andrew Michael Seman ,  Michael Joseph Klodowski

IPC分类号： H05K102

CPC分类号： H05K3/0061 ,  H05K3/321 ,  H05K3/382 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T156/10 ,  Y10T156/1089

摘要： The present invention provides a new device and method for enhancing the electrical properties of the thick metal backer/electrically conductive thermoset adhesive/printed circuit board or card assembly. The enhanced electrical properties are obtained by providing a thin bondline of conductive adhesive that is essentially void free.

公开(公告)号：US5981312A

公开(公告)日：1999-11-09

申请号：US884232

申请日：1997-06-27

申请人： Donald Seton Farquhar ,  Michael Joseph Klodowski ,  Konstantinos Papathomas ,  James Robert Wilcox

发明人： Donald Seton Farquhar ,  Michael Joseph Klodowski ,  Konstantinos Papathomas ,  James Robert Wilcox

IPC分类号： H01L21/60 ,  H01L21/54 ,  H01L21/56 ,  H01L23/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L21/54 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/19107 ,  H01L2924/351

摘要： The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

摘要翻译： 由附接到基板的集成电路芯片组成的集成电路芯片组件的电气连接通过将密封剂材料通过基板中的开口分配到集成电路芯片与集成电路芯片之间的空间中而被高粘度密封剂材料封装并增强 基质。 制造具有加强电互连的集成电路芯片组件，其由于集成电路芯片与集成电路芯片所附接的基板之间的热膨胀系数的差异而产生的应力结果，更能抵抗弱化。

公开(公告)号：US07240430B2

公开(公告)日：2007-07-10

申请号：US11029969

申请日：2005-01-05

申请人： Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

发明人： Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

IPC分类号： H05K3/10

CPC分类号： H05K3/4007 ,  H05K3/06 ,  H05K3/20 ,  H05K3/427 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1572 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

摘要翻译： 一种形成多个固体导电凸块的方法，用于将电路板的两个导电层与基本共面的上表面互连。 该方法包括以下步骤：将连续的均匀金属层施加到电介质基底上，施加第一光致抗蚀剂并暴露和显影所述第一光致抗蚀剂以限定导电凸块的图案，蚀刻由所述显影暴露的金属层以形成所述多个导电 去除所述第一光致抗蚀剂，在所述金属层上施加第二光致抗蚀剂，暴露和显影所述第二光致抗蚀剂以限定导电凸块和电路线的图案; 蚀刻由所述显影曝光的金属层，以在所述金属层中形成电路线图案; 并除去所述第二光致抗蚀剂。 本发明的方法还提供制造用于向面板提供刚性的多层电路板和金属边框。

公开(公告)号：US07063756B2

公开(公告)日：2006-06-20

申请号：US10357950

申请日：2003-02-04

申请人： Donald Seton Farquhar ,  Gerald Paul Kohut ,  Andrew Michael Seman ,  Michael Joseph Klodowski

发明人： Donald Seton Farquhar ,  Gerald Paul Kohut ,  Andrew Michael Seman ,  Michael Joseph Klodowski

IPC分类号： B32B37/04 ,  H05K1/02 ,  H01L21/50 ,  H01L23/00

CPC分类号： H05K3/0061 ,  H05K3/321 ,  H05K3/382 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T156/10 ,  Y10T156/1089

摘要： The present invention provides a new device and method for enhancing the electrical properties of the thick metal backer/electrically conductive thermoset adhesive/printed circuit board or card assembly. The enhanced electrical properties are obtained by providing a thin bondline of conductive adhesive that is essentially void free.