公开(公告)号：US20170250093A1

公开(公告)日：2017-08-31

申请号：US15594794

申请日：2017-05-15

申请人： General Electric Company

发明人： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC分类号： H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

摘要： An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

公开(公告)号：US20160056136A1

公开(公告)日：2016-02-25

申请号：US14464877

申请日：2014-08-21

申请人： General Electric Company

发明人： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC分类号： H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

摘要： An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.

摘要翻译： 一种电子封装包括：第一介电基片，具有通过其厚度形成的第一多个通孔;金属化接触层，其耦合到第一电介质基板的顶表面;以及第一裸片，位于第一裸片开口内， 第一电介质基片。 金属化互连件形成在第一电介质基片的底表面上并延伸通过第一多个通孔以接触金属化的接触层。 第二电介质基板耦合到第一电介质基板，并且具有通过其厚度形成的第二多个通孔。 金属化互连延伸穿过第二多个通孔以接触第一裸片的第一多个金属化互连和接触垫。 第一导电元件将第一裸片电耦合到金属化接触层。

公开(公告)号：US11658070B2

公开(公告)日：2023-05-23

申请号：US17643182

申请日：2021-12-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chiang-Lin Shih ,  Shing-Yih Shih

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/83896 ,  H01L2224/83931

摘要： A method of forming a semiconductor structure includes following steps. A first wafer is bonded to a second wafer, in which the first wafer includes a first substrate and a first conductive pad above a first surface of the first substrate, and the second wafer comprises a second substrate and a second conductive pad above a second surface of the second substrate. A mask layer is formed above the first substrate. The mask layer and the first substrate are etched to form a first opening in the first substrate. A sacrificial spacer is formed in the first substrate at a sidewall of the first opening. The first conductive pad is etched to form a second opening communicated to the first opening. A conductive material is filled in the first opening and the second opening to form a conductive structure interconnecting the first and second conductive pads.

公开(公告)号：US20170365591A1

公开(公告)日：2017-12-21

申请号：US15438184

申请日：2017-02-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： WON-GI CHANG ,  DONGWON LEE ,  MYUNG-SUNG KANG ,  HYEIN YOO

IPC分类号： H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/565 ,  H01L21/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/83201 ,  H01L2224/83931 ,  H01L2224/83947 ,  H01L2225/06544 ,  H01L2924/15311

摘要： A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.

公开(公告)号：US08555491B2

公开(公告)日：2013-10-15

申请号：US12175375

申请日：2008-07-17

申请人： Monnir Boureghda ,  Nitin Desai ,  Anna Lifton ,  Oscar Khaselev ,  Michael T. Marczi ,  Bawa Singh

发明人： Monnir Boureghda ,  Nitin Desai ,  Anna Lifton ,  Oscar Khaselev ,  Michael T. Marczi ,  Bawa Singh

IPC分类号： H05K3/30 ,  H05K3/02 ,  H05K3/10

CPC分类号： H05K13/0465 ,  B22F1/0062 ,  H01L23/373 ,  H01L24/03 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0381 ,  H01L2224/2731 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2936 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/2949 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/83075 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/8321 ,  H01L2224/83211 ,  H01L2224/83438 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83907 ,  H01L2224/8393 ,  H01L2224/83931 ,  H01L2224/8584 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/203 ,  H01L2924/3512 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T428/24893 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/01014

摘要： Methods for attachment of a die to a substrate are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate.

摘要翻译： 公开了将模具附接到基板的方法。 在某些实施例中，该方法包括在衬底上设置封盖的纳米材料，在设置的封盖的纳米材料上设置管芯，干燥所设置的封盖的纳米材料和所设置的管芯，并在300℃的温度下烧结经干燥的设置的管芯和干燥的封盖的纳米材料 ℃以下以将管芯附着到基板上。

公开(公告)号：US11935908B2

公开(公告)日：2024-03-19

申请号：US17327885

申请日：2021-05-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Mihye Jang ,  Seungjoo Nah ,  Minho Jang ,  Heegeun Jeong

IPC分类号： H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H10K39/32

CPC分类号： H01L27/14636 ,  H01L21/76898 ,  H01L24/83 ,  H01L27/14634 ,  H01L27/1469 ,  H10K39/32 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/83931 ,  H01L2224/83951

摘要： An image sensor includes a first structure including a first substrate, and a first internal wiring structure on the first substrate. The first substrate includes an active pixel region and a through electrode region around the active pixel region. The first internal wiring structure includes a plurality of first internal wiring patterns. The image sensor further includes a second structure including a second substrate and a second internal wiring structure on the second substrate. The second substrate is arranged on the first substrate. The image sensor additionally includes a through electrode layer arranged in the through electrode region to at least partially fill a through electrode trench, which penetrates the first substrate, and to connect the first internal wiring structure to the second internal wiring structure.

公开(公告)号：US09847236B2

公开(公告)日：2017-12-19

申请号：US15594794

申请日：2017-05-15

申请人： General Electric Company

发明人： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC分类号： H01L29/80 ,  H01L31/112 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

摘要： An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

公开(公告)号：US20160035702A1

公开(公告)日：2016-02-04

申请号：US14445991

申请日：2014-07-29

申请人： Empire Technology Development LLC

发明人： Zhijiong Luo

IPC分类号： H01L25/065 ,  H01L21/68 ,  H01L25/00 ,  H01L23/528 ,  H01L23/532 ,  H01J37/32 ,  H01L23/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/67 ,  H01L23/373

CPC分类号： H01L25/0657 ,  H01L21/187 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76889 ,  H01L21/8221 ,  H01L23/34 ,  H01L23/36 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L25/50 ,  H01L2021/60007 ,  H01L2021/60097 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27614 ,  H01L2224/27848 ,  H01L2224/29006 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32113 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/325 ,  H01L2224/32503 ,  H01L2224/7525 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/83048 ,  H01L2224/838 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83931 ,  H01L2224/83948 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0474 ,  H01L2924/0475 ,  H01L2924/0476 ,  H01L2924/048 ,  H01L2924/0481 ,  H01L2924/0483 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2224/056 ,  H01L2924/047 ,  H01L2924/00012

摘要： Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

摘要翻译： 通常将技术描述为具有用于散热间隔的集成电路（IC）的三维集成。 根据一些示例，自对准硅化物可以形成在临时硅层中，并且在晶片的结合之后被去除，以通过在IC之间增加的间隔来实现组合IC之间的改善的接触和增强的散热。

公开(公告)号：US20150318255A1

公开(公告)日：2015-11-05

申请号：US14266089

申请日：2014-04-30

申请人： OMKAR G. KARHADE ,  NITIN A. DESHPANDE ,  DANISH FARUQUI

发明人： OMKAR G. KARHADE ,  NITIN A. DESHPANDE ,  DANISH FARUQUI

IPC分类号： H01L23/00 ,  H01L21/306 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/30604 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/83931 ,  H01L2224/83947 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2924/10156 ,  H01L2924/10158 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L21/306

摘要： Ultrathin microelectronic die packages and methods of fabricating the same comprising attaching a microelectronic die to a substrate with a plurality of interconnects, and depositing an underfill material between the microelectronic die and the microelectronic substrate, and around the interconnects. An etchant may be introduced to a back surface of the microelectronic die to remove a portion thereof which reduces the thickness of the microelectronic die to form an ultrathin microelectronic die. In another embodiment, the etching of the microelectronic die forms an ultrathin microelectronic die having a curved surface between the ultrathin microelectronic die back surface and a sidewall thereof.

摘要翻译： 超薄微电子管芯封装及其制造方法包括将微电子管芯附接到具有多个互连的衬底上，以及在微电子管芯和微电子衬底之间以及在互连件周围沉积底部填充材料。 可以将蚀刻剂引入到微电子管芯的后表面以去除其部分，这减少了微电子管芯的厚度以形成超薄微电子管芯。 在另一个实施例中，微电子管芯的蚀刻形成了超薄微电子管芯，其在超薄微电子管芯背表面和其侧壁之间具有弯曲表面。

公开(公告)号：US20240178357A1

公开(公告)日：2024-05-30

申请号：US18088774

申请日：2022-12-27

申请人： AUO Corporation

发明人： Shih-Hsiung Lin

IPC分类号： H01L33/62 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L33/62 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/167 ,  H01L24/06 ,  H01L24/08 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05573 ,  H01L2224/06132 ,  H01L2224/08145 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/245 ,  H01L2224/24991 ,  H01L2224/25174 ,  H01L2224/29016 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/82007 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2924/0549

摘要： A display panel includes a circuit substrate, pixel structures and a molding layer. The circuit substrate has first pad structures and second pad structures. The pixel structures are disposed above a display region of the circuit substrate. Each of at least a portion of the pixel structures includes a first light emitting diode, a first conductive block, and a first conductive connection structure. The first light emitting diode is disposed on a corresponding first pad structure. The first conductive block is disposed on a corresponding second pad structure. The first conductive connection structure electrically connects the first light emitting diode to the first conductive block. The molding layer is located above the circuit substrate and surrounds the first light emitting diode and the first conductive block. The first conductive connection structure is located on the molding layer.