公开(公告)号：US09716141B2

公开(公告)日：2017-07-25

申请号：US14595851

申请日：2015-01-13

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Mark D. Hall ,  Mehul D. Shroff

IPC: H01L29/06 ,  H01L43/02 ,  H01L41/113 ,  H01L29/66 ,  B60C23/00 ,  G01L9/06 ,  H01L33/18 ,  B81B1/00 ,  G01N33/00 ,  G02B6/10 ,  G02B6/126 ,  B82Y40/00 ,  H01L21/308 ,  B82Y30/00 ,  B82Y20/00 ,  G02B6/12

CPC classification number: H01L29/0676 ,  B60C23/00 ,  B81B1/00 ,  B81B2203/0361 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01L9/06 ,  G01N33/0031 ,  G02B6/107 ,  G02B6/126 ,  G02B2006/12097 ,  H01L21/3086 ,  H01L29/0665 ,  H01L29/66 ,  H01L33/18 ,  H01L41/1132 ,  H01L43/02

Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

公开(公告)号：US20170069572A1

公开(公告)日：2017-03-09

申请号：US15256207

申请日：2016-09-02

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  G06F17/5077 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.

Abstract translation: 集成电路器件包括在集成电路器件的第一金属层中的第一线，其中第一线形成互连的至少一部分，集成电路器件的第二金属层中的第二线，以及第一通孔 将第一行耦合到第二行。 集成电路装置还包括布置在互连的第一区域处的第一应力器，其中第一区域至少部分地与第一通孔重叠，其中第一应力器通过改变第一区域处的应力来改变互连的电迁移应力分布 拉力较小。

公开(公告)号：US09515006B2

公开(公告)日：2016-12-06

申请号：US14303128

申请日：2014-06-12

Applicant: Freescale Semiconductor, Inc.

Inventor： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14131 ,  H01L2224/14517 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/81011 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2224/81906 ,  H01L2224/81951 ,  H01L2224/82101 ,  H01L2224/82138 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/12042 ,  H01L2924/15788

Abstract: A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a third surface and a set of metal posts. The first die and the second die are stacked such that the third surface of the second die faces the second surface of the first die, and each metal post extends through a corresponding through-hole to a point beyond the first surface of the first die, electrically coupling the first die and the second die.

Abstract translation: 3D设备封装的方法利用通孔金属柱技术来机械地和电气地粘合两个或更多个骰子。 第一模具包括从第一模具的第一表面延伸到第一模具的第二表面的一组通孔。 第二模具包括第三表面和一组金属柱。 第一模具和第二模具被堆叠成使得第二模具的第三表面面向第一模具的第二表面，并且每个金属支柱延伸通过相应的通孔延伸到超过第一模具的第一表面的点， 电耦合第一管芯和第二管芯。

公开(公告)号：US08946000B2

公开(公告)日：2015-02-03

申请号：US13774486

申请日：2013-02-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5258 ,  H01L23/5256 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.

Abstract translation: 在没有蚀刻的情况下沉积后端行的薄离子束沉积的熔丝（204）以将在后面的金属层（LM）形成的第一和第二金属互连结构（110,120）连接在平面多层互连堆叠 以可编程的方式连接连接到第一和第二金属互连结构的单独的第一和第二电路。

公开(公告)号：US20170084484A1

公开(公告)日：2017-03-23

申请号：US14856772

申请日：2015-09-17

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： DOUGLAS M. REBER ,  Mehul D. Shroff

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/53276 ,  H01L21/28506 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53266

Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

公开(公告)号：US20150363533A1

公开(公告)日：2015-12-17

申请号：US14525342

申请日：2014-10-28

Applicant: Freescale Semiconductor, Inc.

Inventor： Mehul D. Shroff ,  Xavier Hours

IPC: G06F17/50 ,  G05F3/08

CPC classification number: H02M3/158 ,  G05F3/08 ,  G06F17/5036 ,  G06F17/5072 ,  G06F2217/78 ,  H02M2003/1566

Abstract: A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. temperature (PC-T) curves for the electronic device. Each of the one or more PC-T curves indicates, for a particular reliability characteristic limit, a range of power characteristic values over a corresponding range of temperatures that are not expected to result in the reliability characteristic limit being exceeded. Based on the one or more PC-T curves, the design verification system sets a range of power characteristic limits, over a corresponding range of temperatures, for the electronic device. During operation, the electronic device employs a temperature sensor to measure an ambient or device temperature, and sets its power characteristic (voltage or current) according to the measured temperature and the power characteristic limits.

Abstract translation: 设计验证系统模拟电子设备的操作，以识别电子设备的一个或多个功率特性对温度（PC-T）曲线。 对于特定的可靠性特性极限，一个或多个PC-T曲线中的每一个曲线指示在超过预期不会导致可靠性特性极限的相应温度范围内的功率特性值的范围。 基于一个或多个PC-T曲线，设计验证系统在电子设备的相应温度范围内设置功率特性极限的范围。 在操作期间，电子设备采用温度传感器来测量环境温度或器件温度，并根据测量的温度和功率特性限制设置其功率特性（电压或电流）。

公开(公告)号：US09640430B2

公开(公告)日：2017-05-02

申请号：US14856772

申请日：2015-09-17

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Douglas M. Reber ,  Mehul D. Shroff

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L23/53276 ,  H01L21/28506 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53266

Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

公开(公告)号：US09508702B2

公开(公告)日：2016-11-29

申请号：US14169254

申请日：2014-01-31

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Douglas M Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14131 ,  H01L2224/14517 ,  H01L2224/16111 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/014

Abstract: A method for 3D device packaging utilizes through-substrate metal posts to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal posts. The first die and the second die are stacked such that each metal post extends from a surface of the second die toward a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal posts and the corresponding pads.

Abstract translation: 一种用于3D设备封装的方法利用贯穿基板的金属柱来机械地和电气地接合两个或更多个骰子。 第一管芯包括从第一管芯的表面延伸到第一管芯的金属层处的一组焊盘的一组入口孔。 第二个模具包括一组金属柱。 第一模具和第二模具被堆叠，使得每个金属柱从第二模具的表面经由相应的进入孔延伸到相应的焊盘。 第一模具和第二模具通过形成在金属柱和相应焊盘之间的焊接接头进行机械和电连接。

公开(公告)号：US09466569B2

公开(公告)日：2016-10-11

申请号：US14539421

申请日：2014-11-12

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Mehul D. Shroff ,  Douglas M. Reber

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface. A via extends through the substrate. The via is filled with conductive material and extends to at least the first major surface of the substrate. A thermal expansion inhibitor is over and in direct contact with the via proximate the first major surface. The thermal expansion inhibitor exerts a compressive stress on the conductive material closest to the thermal expansion inhibitor compared to the conductive material at a further distance from the thermal expansion inhibitor.

Abstract translation: 半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的半导体衬底。 通孔延伸穿过基板。 通孔填充有导电材料并且延伸至至少衬底的第一主表面。 热膨胀抑制剂在靠近第一主表面的位置处与通孔直接接触。 与距离热膨胀抑制剂更远的距离处的导电材料相比，热膨胀抑制剂对最接近热膨胀抑制剂的导电材料施加压缩应力。

公开(公告)号：US09245817B2

公开(公告)日：2016-01-26

申请号：US14331904

申请日：2014-07-15

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Edward O. Travis ,  Douglas M. Reber ,  Mehul D. Shroff

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/373 ,  H01L21/768 ,  H01L23/3677 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.

Abstract translation: 半导体器件包括半导体衬底和多个时钟驱动器，其中多个时钟驱动器包括半导体器件的基本上所有的时钟驱动器，以及半导体衬底上的互连区域，其中互连区域包括多个散热器， 其中所述多个时钟驱动器中的至少25％具有所述多个散热器中相应的散热器。 多个散热器的每个相应的散热器覆盖多个时钟驱动器的对应的时钟驱动器内的至少50％的晶体管，并延伸到对应的时钟驱动器内的晶体管的周边的至少70％。