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    Method of fabricating a semiconductor IC DRAM device enjoying enhanced focus margin
    1.
    发明授权
    Method of fabricating a semiconductor IC DRAM device enjoying enhanced focus margin 失效
    制造具有增强的聚焦余量的半导体IC DRAM器件的方法

    公开(公告)号：US5670409A

    公开(公告)日：1997-09-23

    申请号：US511810

    申请日：1995-08-07

    申请人： Hiroshi Otori ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Masaharu Kubo ,  Atsuyoshi Koike ,  Fumiyuki Kanai

    发明人： Hiroshi Otori ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Masaharu Kubo ,  Atsuyoshi Koike ,  Fumiyuki Kanai

    IPC分类号： H01L21/304 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10844 ,  H01L27/1052

    摘要： A method of fabricating a semiconductor integrated circuit device includes: recessing a second surface portion of a semiconductor substrate; forming elements of a first circuit region capable of performing a first function at a first surface portion of the semiconductor substrate and elements of a second circuit region capable of performing a second function at the recessed second surface portion of the semiconductor substrate, the elements of the first circuit region and those of the second circuit region having relatively small and large sizes as generally measured in a direction perpendicular to the surface portions of the semiconductor substrate, respectively; forming an insulating film to cover the first and second circuit regions, with a result that a level difference is caused between first and second portions of the insulating film on the first and second circuit regions at a relatively lower level and at a relatively higher level, respectively; effecting chemical-mechanical planarization of the insulating film to suppress the level difference in the insulating film for enhancing a focus margin for successive photolithographic steps; and forming wiring conductors on the insulating film with the suppressed level difference, enjoying the enhanced focus margin.

    摘要翻译： 一种制造半导体集成电路器件的方法包括：使半导体衬底的第二表面部分凹陷; 形成能够在半导体衬底的第一表面部分处执行第一功能的第一电路区域的元件和能够在半导体衬底的凹入的第二表面部分执行第二功能的第二电路区域的元件， 第一电路区域和第二电路区域的第一电路区域分别具有通常在垂直于半导体衬底的表面部分的方向上测量的相对较小和大的尺寸; 形成绝缘膜以覆盖第一和第二电路区域，结果是在第一和第二电路区域上的绝缘膜的第一和第二部分之间在相对较低的电平和相对较高的水平上产生电平差， 分别; 实现绝缘膜的化学机械平面化，以抑制绝缘膜中的水平差，以提高连续光刻步骤的聚焦余量; 并且在绝缘膜上形成具有抑制的电平差的布线导体，享受增强的聚焦余量。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06992343B2

    公开(公告)日：2006-01-31

    申请号：US10975494

    申请日：2004-10-29

    申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

    摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

    摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/比特方法的DRAM具有采用单交叉6F 单元的双单元结构，其结构是：将存储单元布置在与 位线对和字线之间的交点; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。