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公开(公告)号：US08749027B2
公开(公告)日：2014-06-10
申请号：US12349901
申请日：2009-01-07
申请人： Hsien-Wei Chen , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
发明人： Hsien-Wei Chen , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
IPC分类号： H01L23/544 , H01L29/40
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311
摘要： A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure.
摘要翻译： 模具包括在基底下方的密封环结构。 密封环结构围绕至少一个基底区域设置。 至少一种用于基本上防止离子扩散进入衬底区域的装置。 至少一个装置与密封环结构联接。
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公开(公告)号：US20100171203A1
公开(公告)日：2010-07-08
申请号：US12349901
申请日：2009-01-07
申请人： Hsien-Wei CHEN , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
发明人： Hsien-Wei CHEN , Shin-Puu Jeng , Hung-Jung Tu , Wen-Chih Chiou
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311
摘要： A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure.
摘要翻译： 模具包括在基底下方的密封环结构。 密封环结构围绕至少一个基底区域设置。 至少一种用于基本上防止离子扩散进入衬底区域的装置。 至少一个装置与密封环结构联接。
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公开(公告)号：US08105875B1
公开(公告)日：2012-01-31
申请号：US12904835
申请日：2010-10-14
申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L21/50
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号：US08319349B2
公开(公告)日：2012-11-27
申请号：US13342583
申请日：2012-01-03
申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L23/48
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
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公开(公告)号：US08759150B2
公开(公告)日：2014-06-24
申请号：US13488188
申请日：2012-06-04
申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L21/50
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号：US20120238057A1
公开(公告)日：2012-09-20
申请号：US13488188
申请日：2012-06-04
申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L21/60
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
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公开(公告)号：US20120104578A1
公开(公告)日：2012-05-03
申请号：US13342583
申请日：2012-01-03
申请人： Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L23/495
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号：US20120313247A1
公开(公告)日：2012-12-13
申请号：US13157137
申请日：2011-06-09
申请人： Chen-Hua Yu , Shin-Puu Jeng , Wen-Chih Chiou , Fang Wen Tsai , Chen-Yu Tsai
发明人： Chen-Hua Yu , Shin-Puu Jeng , Wen-Chih Chiou , Fang Wen Tsai , Chen-Yu Tsai
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/0217 , H01L21/6835 , H01L21/76831 , H01L21/76834 , H01L21/76871 , H01L21/76895 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2221/68372 , H01L2224/03002 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0347 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05018 , H01L2224/05023 , H01L2224/05025 , H01L2224/05073 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05548 , H01L2224/05559 , H01L2224/05562 , H01L2224/05568 , H01L2224/05647 , H01L2224/13023 , H01L2224/13025 , H01L2224/1411 , H01L2224/14181 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/10253 , H01L2924/01029 , H01L2224/05552
摘要： A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.
摘要翻译： 公开了一种制造硅通孔的系统和方法。 一个实施例包括用从衬底突出的衬垫形成通孔硅通孔。 钝化层形成在衬底和穿通硅通孔之上，钝化层和衬垫从通硅通孔的侧壁凹陷。 然后可以将导电材料形成为与通孔硅通孔的两个侧壁和顶表面接触。
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公开(公告)号：US20120056315A1
公开(公告)日：2012-03-08
申请号：US12874952
申请日：2010-09-02
申请人： Hsin Chang , Fang Wen Tsai , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng
发明人： Hsin Chang , Fang Wen Tsai , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng
IPC分类号： H01L23/48 , H01L21/768 , H01L23/498
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L23/49827 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2223/5442 , H01L2223/54426 , H01L2224/03002 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05647 , H01L2224/11002 , H01L2224/1146 , H01L2224/1147 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01327 , H01L2924/14 , H01L2924/04941 , H01L2924/04953 , H01L2924/00
摘要： A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
摘要翻译： 一种器件包括衬底和包括穿透衬底的导电贯穿衬底通孔（TSV）的对准标记。
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公开(公告)号：US20120001337A1
公开(公告)日：2012-01-05
申请号：US12827563
申请日：2010-06-30
申请人： Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L23/532 , H01L21/71 , H01L23/522
CPC分类号： H01L23/481 , H01L21/30604 , H01L21/6835 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2224/13
摘要： In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
摘要翻译： 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。
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