公开(公告)号：US20200185289A1

公开(公告)日：2020-06-11

申请号：US16463638

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Mitul MODI ,  Robert L. SANKMAN ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Amruthavalli P. ALUR ,  Yikang DENG ,  Eric J. LI

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160300743A1

公开(公告)日：2016-10-13

申请号：US15187729

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Eric J. LI

IPC: H01L21/67 ,  B32B43/00 ,  H01L21/683

CPC classification number: H01L21/67132 ,  B32B43/006 ,  H01L21/67115 ,  H01L21/6836 ,  H01L21/76838 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Vacuum processing, such as a backside metallization (BSM) deposition, is performed on a taped wafer after a gas escape path is formed between a base film of the tape and the wafer frontside surface following backgrind. Venting provided by the gas escape path reduces formation of bubbles under the tape. The gas escape path may be provided, for example, by a selective pre-curing of tape adhesive, to breach an edge seal and place the wafer frontside surface internal to the edge seal in fluid communication with an environment external to the edge seal. With the thinned wafer supported by the pre-cured tape, BSM is then deposited while the wafer and tape are cooled, for example, via a cooled electrostatic chuck.

公开(公告)号：US20240213171A1

公开(公告)日：2024-06-27

申请号：US18596488

申请日：2024-03-05

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20180337135A1

公开(公告)日：2018-11-22

申请号：US15776773

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20220344273A1

公开(公告)日：2022-10-27

申请号：US17861125

申请日：2022-07-08

Applicant: Intel Corporation

Inventor： Toshihiro TOMITA ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20220238402A1

公开(公告)日：2022-07-28

申请号：US17720202

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Mitul MODI ,  Robert L. SANKMAN ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Amruthavalli P. ALUR ,  Yikang DENG ,  Eric J. LI

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200286834A1

公开(公告)日：2020-09-10

申请号：US16879318

申请日：2020-05-20

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20180358296A1

公开(公告)日：2018-12-13

申请号：US15778398

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Eric J. LI ,  Nitin DESHPANDE ,  Shawna M. LIFF ,  Omkar KARHADE ,  Amram EITAN ,  Timothy A. GOSSELIN

IPC: H01L23/538 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

公开(公告)号：US20170200621A1

公开(公告)日：2017-07-13

申请号：US15469284

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE, JR. ,  Aditya Sundoctor VAIDYA ,  Nachiket R. RARAVIKAR ,  Eric J. LI

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.