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    APPARATUS FOR PREVENTION OF MUD HARDENING IN DRAIN HOLDING TANK
    1.
    发明申请
    APPARATUS FOR PREVENTION OF MUD HARDENING IN DRAIN HOLDING TANK 审中-公开
    用于防止排水容器内的泥浆硬化的装置

    公开(公告)号：US20100258486A1

    公开(公告)日：2010-10-14

    申请号：US12822975

    申请日：2010-06-24

    申请人： Ji-Soon Park ,  Young-Ho Jung ,  Young-Beum Jang

    发明人： Ji-Soon Park ,  Young-Ho Jung ,  Young-Beum Jang

    IPC分类号： E21B21/06 ,  C02F1/40 ,  E21B21/01

    CPC分类号： E21B21/063 ,  Y10T137/85954 ,  Y10T137/86035 ,  Y10T137/86131

    摘要： The present invention relates to an apparatus for preventing mud from being hardened in a drain holding tank, in an apparatus that treats drains generated during the marine drilling of petroleum or gas. The apparatus for preventing mud from being hardened in a drain holding tank includes a drain holding tank which gathers a drain being generated in a drilling process; a mud re-compounding pump which circulates a fluid having a pressure that is higher than a predetermined value by spouting the fluid to an area of the drain holding tank where the mud is stored, to prevent mud included in the drain from being hardened in the drain holding tank; a transfer pump which transfers the mud; and a waste mud tank, configured to gather the mud. The apparatus for preventing mud from being hardened in a drain holding tank can circulate the mud at an area of the drain holding tank in which the mud is stored for a period of time, to prevent the mud from being hardened.

    摘要翻译： 本发明涉及一种用于在处理在石油或天然气的海上钻井过程中产生的排水的设备中防止泥浆在排水容器中硬化的装置。 用于防止泥浆在排水容纳槽中硬化的装置包括：排水容纳槽，其收集在钻井过程中产生的排水口; 一种泥浆复合泵，其通过将流体喷射到存储泥浆的排水容纳槽的区域来循环具有高于预定值的压力的流体，以防止包含在排水管中的泥浆在 排水储罐; 输送泥浆的输送泵; 和一个废泥浆池，用于收集泥土。 用于防止泥浆在排水容纳槽中硬化的装置可以在淤泥储存一段时间的排水容纳槽的区域内循环淤泥，以防止泥浆硬化。

    Method for forming tungsten contact plug
    2.
    发明授权
    Method for forming tungsten contact plug 有权
    形成钨接触塞的方法

    公开(公告)号：US07199019B2

    公开(公告)日：2007-04-03

    申请号：US11002682

    申请日：2004-12-03

    申请人： Ji-Soon Park ,  Hyun-Seok Lim ,  Eung-Joon Lee ,  Jung-Wook Kim

    发明人： Ji-Soon Park ,  Hyun-Seok Lim ,  Eung-Joon Lee ,  Jung-Wook Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/28562 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76876 ,  H01L21/76879 ,  H01L2221/1089

    摘要： A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.

    摘要翻译： 一种用于形成半导体器件的钨接触插塞的方法，包括在半导体衬底上沉积绝缘层，蚀刻绝缘层以形成接触孔，其暴露导电区域，在具有接触孔的半导体衬底上形成阻挡层 改变绝缘层上的阻挡层的一部分和接触保持部中阻挡层的部分的特性，使得绝缘层上的阻挡层与接触孔中的阻挡层之间的特性不同，沉积钨 在阻挡层上形成钨接触塞的层，以及从绝缘层的上部去除钨层以使半导体器件平坦化。

    NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权
    非易失性存储器件

    公开(公告)号：US20120120728A1

    公开(公告)日：2012-05-17

    申请号：US13191581

    申请日：2011-07-27

    申请人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

    发明人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

    IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

    摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

    摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

    Method of forming polycide layer and method of manufacturing semiconductor device having polycide layer
    6.
    发明申请
    Method of forming polycide layer and method of manufacturing semiconductor device having polycide layer 审中-公开
    形成聚酰亚胺层的方法和制造具有多晶硅化物层的半导体器件的方法

    公开(公告)号：US20060281289A1

    公开(公告)日：2006-12-14

    申请号：US11446981

    申请日：2006-06-06

    申请人： Young-Cheon Kim ,  Chul Hwangbo ,  Rak-Hwan Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

    发明人： Young-Cheon Kim ,  Chul Hwangbo ,  Rak-Hwan Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/26513 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/7833

    摘要： In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into a portion of the preliminary polysilicon layer on the second region, heat treating the preliminary polysilicon layer to electrically activate the impurities, removing a portion of an upper surface of the heat treated preliminary polysilicon layer to obtain a polysilicon layer, forming a metal silicide layer on the polysilicon layer, and patterning the polysilicon layer and the metal silicide layer to form a first type gate electrode on the first region and to form a second type gate electrode on the second region.

    摘要翻译： 在形成多晶硅化合物层的方法和制造具有多晶硅化物层的半导体器件的方法中，该方法可以包括在具有第一区域和第二区域的衬底上形成掺杂有第一类型杂质的初步多晶硅层， 杂质进入第二区域的初步多晶硅层的一部分，热处理初步多晶硅层以电激活杂质，去除热处理的初步多晶硅层的上表面的一部分以获得多晶硅层，形成金属硅化物 并且在所述第一区域上形成所述多晶硅层和所述金属硅化物层以形成第一类型的栅电极，并在所述第二区域上形成第二类型的栅电极。

    Method for forming silicide film of a semiconductor device
    7.
    发明授权
    Method for forming silicide film of a semiconductor device 失效
    半导体器件的硅化物膜的形成方法

    公开(公告)号：US06797618B2

    公开(公告)日：2004-09-28

    申请号：US10630570

    申请日：2003-07-29

    申请人： Eung-Joon Lee ,  In-Sun Park ,  Ji-Soon Park

    发明人： Eung-Joon Lee ,  In-Sun Park ,  Ji-Soon Park

    IPC分类号： H01L2144

    CPC分类号： H01L21/0206 ,  H01L21/02063 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/665 ,  Y10S438/906 ,  Y10S438/963

    摘要： A conductive pattern having a surface including silicon is formed on a substrate of a semiconductor device and a conduction region having a surface including silicon is formed in the substrate. A radio frequency etching process is performed ex-situ to remove impurities from a resultant structure and to improve surface characteristics of the conduction region. Residues generated during the radio frequency etching process are removed from the conductive pattern and the conduction region by a cleaning process. A metal film is formed on the conductive pattern and the conduction region. A silicide film is formed on the conductive pattern and the conduction region by reacting metal of the metal film and silicon in the conductive pattern and the conduction region. With a radio frequency sputtering process and a wet cleaning process, a metal silicide film having a uniform phase may be stably formed.

    摘要翻译： 在半导体器件的衬底上形成具有包括硅的表面的导电图案，并且在衬底中形成具有包括硅的表面的导电区域。 非原位地进行射频蚀刻处理以从所得结构中去除杂质并改善导电区域的表面特性。 在射频蚀刻工艺中产生的残留物通过清洁处理从导电图案和导电区域中去除。 在导电图案和导电区域上形成金属膜。 通过金属膜的金属和导电图案中的硅和导电区域之间的反应，在导电图案和导电区域上形成硅化物膜。 通过射频溅射法和湿式清洗法，可以稳定地形成具有均匀相的金属硅化物膜。

    Semiconductor device conductive pattern structures and methods of manufacturing the same
    8.
    发明授权
    Semiconductor device conductive pattern structures and methods of manufacturing the same 有权
    半导体器件导电图案结构及其制造方法

    公开(公告)号：US08592979B2

    公开(公告)日：2013-11-26

    申请号：US13440123

    申请日：2012-04-05

    申请人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

    发明人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/11524 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.

    摘要翻译： 导电图案结构包括在基板上的第一绝缘中间层，第一绝缘中间层上的金属布线，金属布线上的第二绝缘中间层以及延伸穿过第二绝缘夹层的第一和第二金属触点。 第一金属触点与单元区域中的金属布线接触，并且第二金属触点与外围区域中的金属布线接触。 第三绝缘中间层设置在第二绝缘中间层上。 导电部分延伸通过电池区域中的第三绝缘中间层并与第一金属触点接触。 另一个导电段延伸穿过周边区域中的第三绝缘中间层并接触第二金属接触。 该结构有助于使用电镀工艺在电池区域中形成均匀厚的布线。