公开(公告)号：US5268330A

公开(公告)日：1993-12-07

申请号：US989604

申请日：1992-12-11

申请人： John H. Givens ,  James S. Nakos ,  Peter A. Burke ,  Craig M. Hill ,  Chung H. Lam

发明人： John H. Givens ,  James S. Nakos ,  Peter A. Burke ,  Craig M. Hill ,  Chung H. Lam

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L21/283 ,  H01L21/302

CPC分类号： H01L21/321 ,  H01L21/76802 ,  Y10S438/934

摘要： A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of the passivating layer above the gate is removed with little or no effect on the insulating layer or gate. A trench above one or both junctions (source or drain) is formed by removing insulation using the passivating layer as an etch stop, then removing a portion of the passivating layer above the junction with little or no effect on the junction or any isolation region present. The gate may be further silicided, and the opening above the gate and the trench above the junction may each be planarly filled with a low sheet resistance conductive material, forming contacts. The contact above the junction may be borderless.

公开(公告)号：US5185294A

公开(公告)日：1993-02-09

申请号：US797506

申请日：1991-11-22

申请人： Chung H. Lam ,  Jerome B. Lasky ,  Craig M. Hill ,  James S. Nakos ,  Steven J. Holmes ,  Stephen F. Geissler ,  David K. Lord

发明人： Chung H. Lam ,  Jerome B. Lasky ,  Craig M. Hill ,  James S. Nakos ,  Steven J. Holmes ,  Stephen F. Geissler ,  David K. Lord

IPC分类号： H01L21/28 ,  H01L21/223 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H01L29/43

CPC分类号： H01L21/32134 ,  H01L21/768

摘要： The invention provides a method for electrically connecting a polysilicon-filled trench to a diffusion region in a semiconductor device, wherein the trench and diffusion region are separated by a dielectric. The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer which prevents diffusion into an overlying polysilicon layer when a subsequent boron out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.

公开(公告)号：US06256755B1

公开(公告)日：2001-07-03

申请号：US09174789

申请日：1998-10-19

申请人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

发明人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

IPC分类号： G11C2900

CPC分类号： G11C16/349 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012

摘要： An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

摘要翻译： 一种用于检测NVRAM单元的不良阵列的装置和方法。 在常规擦除功能期间提供计数器，其为NVRAM单元的擦除时间间隔。 计算的擦除间隔与最大擦除间隔进行比较，以确定至少第一特性，其指示NVRAM的块处于其使用寿命的结束。 通过计算擦除时间函数中的斜率与模拟擦除函数的数量来确定第二特性。 当擦除功能的斜率超过最大斜率时，NVRAM阵列被确定为其使用寿命结束。

公开(公告)号：US5521118A

公开(公告)日：1996-05-28

申请号：US440574

申请日：1995-05-15

申请人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

发明人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

CPC分类号： H01L27/10861 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90

摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

摘要翻译： 本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。 侧壁连接器具有包括外表面的顶部部分。 导电构件接触顶部，将轨道连接到导电区域或外部导体。 位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。 然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。 通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。 连接器用于形成用于DRAM单元的带子。

公开(公告)号：US08902690B2

公开(公告)日：2014-12-02

申请号：US13584423

申请日：2012-08-13

申请人： Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

发明人： Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC分类号： G11C8/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/004 ,  G11C2213/71 ,  G11C2213/72

摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

公开(公告)号：US08687398B2

公开(公告)日：2014-04-01

申请号：US13407813

申请日：2012-02-29

申请人： Leland Chang ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

发明人： Leland Chang ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.

摘要翻译： 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间，将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

公开(公告)号：US20140052900A1

公开(公告)日：2014-02-20

申请号：US13610830

申请日：2012-09-11

申请人： Bing Dai ,  Chung H. Lam ,  Jing Li

发明人： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC分类号： G06F12/02

CPC分类号： G06F12/02 ,  G06F1/32 ,  G06F12/0246

摘要： A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

公开(公告)号：US20130314983A1

公开(公告)日：2013-11-28

申请号：US13478932

申请日：2012-05-23

申请人： Chung H. Lam ,  Jing Li ,  Binquan Luan ,  Glenn J. Martyna ,  Dennis M. Newns

发明人： Chung H. Lam ,  Jing Li ,  Binquan Luan ,  Glenn J. Martyna ,  Dennis M. Newns

IPC分类号： G11C11/00 ,  H01L47/00

CPC分类号： G11C11/16 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit.

公开(公告)号：US08536675B2

公开(公告)日：2013-09-17

申请号：US13364153

申请日：2012-02-01

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

IPC分类号： H01L23/52 ,  H01L29/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。

公开(公告)号：US08421194B2

公开(公告)日：2013-04-16

申请号：US13006403

申请日：2011-01-13

申请人： Chung H. Lam ,  Hemantha K. Wickramasinghe

发明人： Chung H. Lam ,  Hemantha K. Wickramasinghe

IPC分类号： H01L29/06

CPC分类号： H01L21/0337

摘要： A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.

摘要翻译： 沟槽结构和集成电路，其包括衬底中的次光刻沟槽结构。 在一个实施例中，沟槽结构是通过用光刻掩膜形成一组沟槽而形成的，并且用一组间隔块块填充该组沟槽，该组间隔块包括彼此分离地可拆卸的两个交替间隔物材料。 在一个实施例中，形成的沟槽结构是光刻掩模的特征尺寸的厚度的十分之一。 沟槽结构的尺寸取决于用于形成一组步进间隔块的间隔材料层的厚度和数量。 间隔材料层的数量为n / 2，每个间隔材料层的厚度为光刻掩模的特征尺寸的十分之一。