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18 条记录 (耗时 0.024 秒)

    Direct backside interconnect for multiple chip assemblies
    7.
    发明授权
    Direct backside interconnect for multiple chip assemblies 失效
    用于多个芯片组件的直接背面互连

    公开(公告)号：US06175287B1

    公开(公告)日：2001-01-16

    申请号：US08864533

    申请日：1997-05-28

    申请人： James L. Lampen ,  Paul Setzco ,  Thomas E. Kazior ,  Michael G. Kizner ,  John P. Wendler, Jr.

    发明人： James L. Lampen ,  Paul Setzco ,  Thomas E. Kazior ,  Michael G. Kizner ,  John P. Wendler, Jr.

    IPC分类号： H01L2302

    CPC分类号： H01L23/66 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2924/0002 ,  H01L2924/1423 ,  H01L2924/15192 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A plurality of integrated circuits, such as microwave monolithic integrated circuits (MMICs), is supported upon a common carrier substrate having transmission lines for interconnection of signals between terminals of any one of the MMICs and among terminals of the plurality of MMICs. Circuit terminals at the front sides of the respective MMICs are connected electrically by vias to the back sides of the respective MMICs to be adjacent conductive components of the transmission lines. Electrically conductive bumps of metal or epoxy serve to connect the vias to the conductive components of the transmission lines, and to connect also metallized regions of the MMICs to metallized regions of the substrate.

    摘要翻译： 诸如微波单片集成电路（MMIC）的多个集成电路被支撑在具有用于互连MMIC中的任一个的终端之间以及多个MMIC的终端之间的信号互连的传输线的公共载体衬底上。 各个MMIC的前侧的电路端子通过通孔与相应的MMIC的背面电连接成与传输线路相邻的导电部件。 金属或环氧树脂的导电凸块用于将通孔连接到传输线的导电部件，并将MMIC的金属化区域连接到衬底的金属化区域。

    Semiconductor structures having dual surface via holes
    8.
    发明授权
    Semiconductor structures having dual surface via holes 失效
    具有双面通孔的半导体结构

    公开(公告)号：US5343071A

    公开(公告)日：1994-08-30

    申请号：US54380

    申请日：1993-04-28

    申请人： Thomas E. Kazior ,  John C. Huang

    发明人： Thomas E. Kazior ,  John C. Huang

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L27/06 ,  H01L29/417 ,  H01L29/06

    CPC分类号： H01L29/4175 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0605 ,  H01L2924/0002 ,  H01L2924/10158

    摘要： A semiconductor structure having an active layer formed over a first surface of a substrate. The semiconductor structure includes an electrode formed over a first surface of the structure. A conductive layer is formed over a second surface of the substrate. A conductor section passes through the semiconductor structure between the electrode and the conductive layer. The conductor section includes two conductive elements, one having a first end connected to the electrode and a second end terminating in the semiconductor structure; and the other conductive element having a first end connected to the conductive layer and a second end connected to the second end of the first conductive element. The second end terminates at, or in, an etch resistant layer disposed in the semiconductor structure between the active layer and the substrate. The method for forming the conductive sections includes etching the second via hole from the second surface of the substrate until the etching reaches an etch resistant layer. The walls of the second via hole and exposed portions of the conductive material covering the walls of the first via hole are covered with an electrically conductive material.

    摘要翻译： 一种在衬底的第一表面上形成的有源层的半导体结构。 半导体结构包括形成在该结构的第一表面上的电极。 在衬底的第二表面上形成导电层。 导体部分穿过电极和导电层之间的半导体结构。 导体部分包括两个导电元件，一个具有连接到电极的第一端和终止在半导体结构中的第二端; 并且另一导电元件具有连接到导电层的第一端和连接到第一导电元件的第二端的第二端。 第二端终止于设置在有源层和衬底之间的半导体结构中的耐蚀刻层，或其中。 用于形成导电部分的方法包括从衬底的第二表面蚀刻第二通孔，直到蚀刻到达耐蚀刻层。 第二通孔的壁和覆盖第一通孔的壁的导电材料的暴露部分被导电材料覆盖。

    Selective backside plating of gaas monolithic microwave integrated circuits
    9.
    发明授权
    Selective backside plating of gaas monolithic microwave integrated circuits 失效
    高斯单片微波集成电路的选择性背面电镀

    公开(公告)号：US4794093A

    公开(公告)日：1988-12-27

    申请号：US44685

    申请日：1987-05-01

    申请人： Elsa K. Tong ,  Thomas E. Kazior

    发明人： Elsa K. Tong ,  Thomas E. Kazior

    IPC分类号： H01L21/308 ,  H01L21/74 ,  H01L23/367 ,  H01L23/48 ,  H01L19/00

    CPC分类号： H01L21/743 ,  H01L21/308 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/10329 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/105 ,  Y10S148/135

    摘要： A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium. Preferably, the gold is plated to completely or substantially completely fill the tub. The vias are then provided on the backside of the wafer by masking the first continuous conductive coating and the tub regions and etching the unexposed regions of the substrate to provide the via holes. The via holes are then plated with a continuous conductive layer of palladium and then gold to substantially fill the via.

    摘要翻译： 描述了在由砷化镓构成的晶片的背面上蚀刻槽结构和通孔并在砷化镓晶片的所述背面上提供平坦表面的技术。 通过在砷化镓衬底的背面上提供一层抗蚀剂来形成桶体，并且对该层进行图案化，以提供覆盖其中将提供桶结构和通孔的区域的选定区域。 在选择性暴露的区域中，依次沉积钯和金。 然后剥离抗蚀剂图案，并且沉积第二抗蚀剂层图案，掩蔽连续导电层的掩模部分和要设置通孔的区域。 然后通过适当地蚀刻桶以将抗蚀剂和钯层的部分倒下来提供浴缸结构。 然后在桶结构中提供第二连续导电涂层以提供用于随后在钯上镀覆金膜的镀层。 优选地，金被镀以完全或基本上完全填充桶。 然后通过掩蔽第一连续导电涂层和桶区并且蚀刻基板的未曝光区域以提供通孔，将通孔设置在晶片的背面。 然后将通孔用镀钯的连续导电层然后镀金，以基本上填充通孔。

    METHOD AND STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR
    10.
    发明申请
    METHOD AND STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR 有权
    具有单体半导体的化合物半导体的单晶异质性整合的方法和结构

    公开(公告)号：US20130082281A1

    公开(公告)日：2013-04-04

    申请号：US13249579

    申请日：2011-09-30

    申请人： Jeffrey R. LaRoche ,  Thomas E. Kazior ,  William E. Hoke

    发明人： Jeffrey R. LaRoche ,  Thomas E. Kazior ,  William E. Hoke

    IPC分类号： H01L29/16 ,  H01L29/20 ,  H01L27/12 ,  H01L27/092

    CPC分类号： H01L21/8258 ,  H01L27/1207

    摘要： A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

    摘要翻译： 具有形成在该结构的化合物半导体中的化合物半导体（CS）器件的半导体结构和形成在该结构的元素半导体层中的元素半导体器件。 该结构包括具有元素半导体器件的层设置在掩埋氧化物（BOX）层上。 选择性蚀刻层设置在BOX层和化合物半导体器件的层之间。 选择性蚀刻层能够选择性地蚀刻BOX层，从而最大化在蚀刻窗口中生长的化合物半导体器件的垂直和侧向窗蚀刻工艺控制。 选择性蚀刻层具有比BOX层的蚀刻速率更低的蚀刻速率。