公开(公告)号：US20110101516A1

公开(公告)日：2011-05-05

申请号：US12590138

申请日：2009-11-03

申请人： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

发明人： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

IPC分类号： H01L23/10 ,  H01L21/00 ,  H01L21/66

CPC分类号： H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

摘要翻译： 微电子封装包括具有第一表面区域（125）的第一衬底（120）和具有第二表面区域（135）的第二衬底（130）。 第一衬底包括在第一表面处具有第一间距（127）的第一组互连（126）和在第二表面（222）处具有第二间距（129）的第二组互连（128）。 第二衬底使用第二组互连件耦合到第一衬底，并且包括具有第三间距（237）和第三组互连（236）的第三组互连（236），并且内部导电层（233,234）以微孔（ 240）。 第一间距小于第二间距，第二间距小于第三间距，第一表面积小于第二表面积。

公开(公告)号：US08035218B2

公开(公告)日：2011-10-11

申请号：US12590138

申请日：2009-11-03

申请人： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

发明人： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

公开(公告)号：US20110318850A1

公开(公告)日：2011-12-29

申请号：US13225745

申请日：2011-09-06

申请人： John S. Guzek ,  Mahadevan Suryakumar ,  Hamid R. Azimi

发明人： John S. Guzek ,  Mahadevan Suryakumar ,  Hamid R. Azimi

IPC分类号： H01L21/66

CPC分类号： H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

摘要翻译： 微电子封装包括具有第一表面区域（125）的第一衬底（120）和具有第二表面区域（135）的第二衬底（130）。 第一衬底包括在第一表面处具有第一间距（127）的第一组互连（126）和在第二表面（222）处具有第二间距（129）的第二组互连（128）。 第二衬底使用第二组互连件耦合到第一衬底，并且包括具有第三间距（237）和第三组互连（236）的第三组互连（236），并且内部导电层（233,234）以微孔（ 240）。 第一间距小于第二间距，第二间距小于第三间距，第一表面积小于第二表面积。

公开(公告)号：US20140084467A1

公开(公告)日：2014-03-27

申请号：US14090461

申请日：2013-11-26

申请人： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

发明人： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC分类号： H01L21/56 ,  H01L23/498

CPC分类号： H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：US09526285B2

公开(公告)日：2016-12-27

申请号：US13717909

申请日：2012-12-18

申请人： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Sairam Agraharam ,  Ian A. Young ,  John C. Johnson ,  Debendra Mallik ,  John S. Guzek

发明人： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Sairam Agraharam ,  Ian A. Young ,  John C. Johnson ,  Debendra Mallik ,  John S. Guzek

IPC分类号： H05K1/02 ,  H05K3/30 ,  A41D31/00 ,  H05K1/03 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34

CPC分类号： A41D31/00 ,  H05K1/0274 ,  H05K1/038 ,  H05K1/188 ,  H05K3/323 ,  H05K3/3436 ,  Y10T29/4913

摘要： A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.

摘要翻译： 一种灵活的计算结构及其形成方法。 柔性计算结构包括包括一个或多个通道并且包括至少两个端部的电子基板。 至少一个计算元件安装在两端之间的电子基板上，并且至少一个功能元件安装在两端之间的电子基板上。 通道形成元件之间的互连。 此外，电子基板是柔性的并且具有在0.1GPa至30GPa范围内的挠曲模量。

公开(公告)号：US09224674B2

公开(公告)日：2015-12-29

申请号：US13996495

申请日：2011-12-15

申请人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

发明人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

IPC分类号： H01L27/08 ,  H01L23/552 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L24/09 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

公开(公告)号：US20150171065A1

公开(公告)日：2015-06-18

申请号：US14104877

申请日：2013-12-12

申请人： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

发明人： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

摘要： Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了允许诸如处理器和存储器的设备之间的相对短的连接的集成电路封装组件。 在一个实施例中，封装组件包括嵌入到直接耦合到附接到子封装的另一管芯的子封装中的管芯。 在一些实施例中，子包还可以包含电源管理装置。 在一些实施例中，嵌入在子封装和/或功率管理器件中的管芯可以与耦合到子封装的管芯定义的区域重叠或位于其中，使得它们位于耦合到子封装的管芯和衬底之间 子包。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20100301492A1

公开(公告)日：2010-12-02

申请号：US12857332

申请日：2010-08-16

申请人： Sriram Muthukumar ,  Nicholas R. Watts ,  John S. Guzek

发明人： Sriram Muthukumar ,  Nicholas R. Watts ,  John S. Guzek

IPC分类号： H01L23/522

CPC分类号： H01L23/49822 ,  H01L2224/0554 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0271 ,  H05K3/28 ,  H05K3/4682 ,  H05K2203/0582 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

摘要翻译： 本发明的实施例涉及一种加强半导体无芯封装基板以提高刚性和抗翘曲性的方法。 该方法的一个实施例包括在无芯封装基板的第二级互连（封装 - 板间互连）侧上的多个接触焊盘上设置牺牲掩模，在牺牲掩模周围形成模制的加强件，而不增加有效厚度 并且去除牺牲掩模以在对应于接触焊盘的模制加强件中形成多个空腔。 实施例还包括用导电材料电镀接触垫的表面和模制空腔中的空腔的侧壁。

公开(公告)号：US09368455B2

公开(公告)日：2016-06-14

申请号：US14229771

申请日：2014-03-28

申请人： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elsherbini ,  Nitin Ashok Deshpande

发明人： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elsherbini ,  Nitin Ashok Deshpande

IPC分类号： H01L23/00 ,  H01L23/552 ,  H01L21/56

CPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/81

摘要： An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a package has a semiconductor die. a redistribution layer, a mold compound over the die, a plurality of vias through the mold compound and outside the die to form a shield, and a metal film over the vias. and over the mold compound.

摘要翻译： 半导体芯片封装描述了电磁干扰屏蔽。 在一些实施例中，封装具有半导体管芯。 再分布层，模具上的模具化合物，通过模具化合物的多个通孔和模具外部以形成屏蔽，以及在通孔上方的金属膜。 并在模具化合物上。

公开(公告)号：US20150279789A1

公开(公告)日：2015-10-01

申请号：US14229771

申请日：2014-03-28

申请人： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elshebini ,  Nitin Ashok Deshpande

发明人： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elshebini ,  Nitin Ashok Deshpande

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/81

摘要： An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a package has a semiconductor die. a redistribution layer, a mold compound over the die, a plurality of vias through the mold compound and outside the die to form a shield, and a metal film over the vias. and over the mold compound.

摘要翻译： 半导体芯片封装描述了电磁干扰屏蔽。 在一些实施例中，封装具有半导体管芯。 再分布层，模具上的模具化合物，通过模具化合物的多个通孔和模具外部以形成屏蔽，以及在通孔上方的金属膜。 并在模具化合物上。