Method of manufacturing a semiconductor device
    2.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US20090011583A1

    公开(公告)日:2009-01-08

    申请号:US12165805

    申请日:2008-07-01

    IPC分类号: H01L21/28

    摘要: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

    摘要翻译: 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后,在层间绝缘层上直接形成氮化硅层,在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前,可以通过与基板接触的第一绝缘中间层形成插塞,并且金属布线可以电连接到插头。 插头可以包括钨。

    Method of manufacturing a semiconductor device
    3.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US07972941B2

    公开(公告)日:2011-07-05

    申请号:US12165805

    申请日:2008-07-01

    IPC分类号: H01L21/322

    摘要: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

    摘要翻译: 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后,在层间绝缘层上直接形成氮化硅层,在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前,可以通过与基板接触的第一绝缘中间层形成插塞,并且金属布线可以电连接到插头。 插头可以包括钨。

    Nonvolatile memory device and method for forming the same
    4.
    发明申请
    Nonvolatile memory device and method for forming the same 审中-公开
    非易失存储器件及其形成方法

    公开(公告)号:US20080093663A1

    公开(公告)日:2008-04-24

    申请号:US11882654

    申请日:2007-08-03

    IPC分类号: H01L21/336 H01L29/792

    摘要: A method of forming a memory device includes forming a first insulating pattern and a polysilicon pattern in a peripheral region of a substrate, forming a cell gate insulating pattern including a second insulating pattern, a charge storage pattern, and a third insulating pattern in a cell region of the substrate, forming a barrier metal layer on the polysilicon pattern and on the third insulating pattern, forming a conductive layer on the barrier metal layer, patterning the conductive layer to simultaneously form a first conductive pattern on the polysilicon pattern and a second conductive pattern on the third insulating pattern, and patterning the barrier metal layer to simultaneously form a first barrier metal pattern on the polysilicon pattern and a second barrier metal pattern on the third insulating pattern.

    摘要翻译: 形成存储器件的方法包括在衬底的周边区域中形成第一绝缘图案和多晶硅图案,在单元中形成包括第二绝缘图案,电荷存储图案和第三绝缘图案的单元栅极绝缘图案 在所述多晶硅图案和所述第三绝缘图案上形成阻挡金属层,在所述阻挡金属层上形成导电层,图案化所述导电层以同时在所述多晶硅图案上形成第一导电图案,并且将第二导电 图案化所述阻挡金属层,同时在所述多晶硅图案上形成第一阻挡金属图案,以及在所述第三绝缘图案上形成第二阻挡金属图案。

    Methods for fabricating improved gate dielectrics
    5.
    发明授权
    Methods for fabricating improved gate dielectrics 有权
    制造改进的栅极电介质的方法

    公开(公告)号:US07879737B2

    公开(公告)日:2011-02-01

    申请号:US12801115

    申请日:2010-05-24

    IPC分类号: H01L21/31

    摘要: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译: 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案,并提供改进的耐漏电性,而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域,在暴露部分上形成氧化控制区域,然后形成第二开口,由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

    Semiconductor memory device and method of manufacturing the same
    6.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号:US07585787B2

    公开(公告)日:2009-09-08

    申请号:US11648595

    申请日:2007-01-03

    IPC分类号: H01L21/469

    摘要: A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

    摘要翻译: 半导体存储器件,例如电荷俘获型非易失性存储器件,可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。 电荷捕获结构可以包括隧道氧化物层图案,电荷俘获层图案和含铝三级金属氧化物的介电层图案。 栅极结构可以包括栅极氧化物层图案,多晶硅层图案和含铝三次金属硅化物的欧姆层图案。 第一电极和第二电极可以形成在电荷捕获结构上。 可以在栅极结构上设置下电极和上电极。 电介质层图案可以具有更高的介电常数,并且欧姆层图案可以具有改善的热稳定性,从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

    Methods for fabricating improved gate dielectrics
    8.
    发明授权
    Methods for fabricating improved gate dielectrics 失效
    制造改进的栅极电介质的方法

    公开(公告)号:US07759263B2

    公开(公告)日:2010-07-20

    申请号:US11806338

    申请日:2007-05-31

    IPC分类号: H01L21/336

    摘要: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译: 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案,并提供改进的耐漏电性,而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域,在暴露部分上形成氧化控制区域,然后形成第二开口,由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

    Semiconductor memory device and method of manufacturing the same
    9.
    发明申请
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号:US20080079056A1

    公开(公告)日:2008-04-03

    申请号:US11648595

    申请日:2007-01-03

    IPC分类号: H01L29/76

    摘要: A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

    摘要翻译: 半导体存储器件,例如电荷俘获型非易失性存储器件,可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。 电荷捕获结构可以包括隧道氧化物层图案,电荷俘获层图案和含铝三级金属氧化物的介电层图案。 栅极结构可以包括栅极氧化物层图案,多晶硅层图案和含铝三次金属硅化物的欧姆层图案。 第一电极和第二电极可以形成在电荷捕获结构上。 可以在栅极结构上设置下电极和上电极。 电介质层图案可以具有更高的介电常数,并且欧姆层图案可以具有改善的热稳定性,从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

    Methods for fabricating improved gate dielectrics
    10.
    发明申请
    Methods for fabricating improved gate dielectrics 失效
    制造改进的栅极电介质的方法

    公开(公告)号:US20080014700A1

    公开(公告)日:2008-01-17

    申请号:US11806338

    申请日:2007-05-31

    IPC分类号: H01L21/336

    摘要: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译: 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案,并提供改进的耐漏电性,而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域,在暴露部分上形成氧化控制区域,然后形成第二开口,由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。